RISC-VAvailable
RV32I with the M extension: assembler, C-subset compiler, and single-cycle, multicycle and five-stage pipelined processors animated on their datapaths.
Address: /mavilera/riscv/
Interactive Microprocessor Architecture Laboratory
Visualize. Execute. Understand.
MAVILERA is an open-source educational platform for exploring microprocessor architecture through interactive simulation, visualization, and instruction execution.
Runs entirely in your browser: no account, no installation, and no program or data is uploaded.
Architectures
Each architecture is a separate simulator with its own address. Only the available ones can be launched.
SAP-1Available
The simple-as-possible computer: five instructions, sixteen bytes of memory, an accumulator and an adder-subtracter on one bus, each instruction stepped through its six timing states on a drawing of the bus and its controller.
Address: /mavilera/sap-1/
SAP-2Available
The simple-as-possible computer, version 2: 43 instructions, 64K bytes of memory, a flag pair, CALL and RET, and input and output ports with a keys-and-serial panel; each instruction stepped through its timing states on a drawing of the bus and its controller.
Address: /mavilera/sap-2/
MOS 6502Planned
Not yet available.
Not yet available
Intel 8086Planned
Not yet available.
Not yet available
Armv7Planned
Not yet available.
Not yet available
MIPSPlanned
Not yet available.
Not yet available
Learning by observing
These are the activities the laboratories support today.
RISC-V Laboratory
Interactive execution
Assemble a program, then step forwards and backwards, run to a breakpoint or a watchpoint, and see each instruction's effect.
Datapath observation
Single-cycle, multicycle and five-stage pipelined processors, animated signal by signal on their datapath drawings.
Processor-state inspection
Registers, memory, call stack, counters and the console, updated as the program runs.
Control-flow visualization
The controller's state diagram, the pipeline diagram, forwarding, stalls, flushes and branch prediction.
Experiments with instructions
Short teaching programs and practice exercises, each opening in the view that shows its idea; a comparison of one program on the three processors.
SAP-1 Laboratory
One bus, six timing states
Each instruction stepped clock by clock through its fetch and execute states on a drawing of the bus, the registers and the controller, with the control word of every state.
Programming the simple-as-possible computer
Five instructions in sixteen bytes of memory: assemble, step forwards and backwards, run to a breakpoint or a watched register, and encode or decode a byte.
Waveforms and files
The control signals, the bus and the registers as waveforms and VCD; memory images, traces, a dump of the output, and data files loaded into a program.
Practice exercises
Short tasks with tests that run on your program and show expected against actual values.
SAP-2 Laboratory
Instruction by instruction, state by state
Forty-three instructions with their timing states, stepped on a drawing of the bus, the registers and the controller, with the microinstruction and the signals of every state.
Programming with ports and subroutines
Sixty-four kilobytes of memory with a read-only region, two flags, CALL and RET, and input and output ports: assemble, step forwards and backwards, run to a breakpoint, and encode or decode bytes.
Keys, serial ports and files
A panel of keys and a serial switch that feed the input ports, with the output ports shown as bytes and bits; waveforms, VCD, memory images, traces and a dump of the port writes and memory.
Templates and practice exercises
Short programs that open in the view that shows their idea, and tasks with tests that run on your program and show expected against actual values.
A simulation is a teaching model; it is not evidence of how a hardware implementation behaves. Tested browsers for this release: Chrome 156. Only the browsers listed were tested.
Download the single-file offline version of the RISC-V Laboratory (1738 kB) · Download the single-file offline version of the SAP-1 Laboratory (704 kB) · Download the single-file offline version of the SAP-2 Laboratory (748 kB) · validation record
About
MAVILERA stands for Microprocessor Architecture Visualizer for Interactive Learning, Execution, and Runtime Analysis. It is written by Sajid Muhaimin Choudhury. The simulators are independent of one another: each has its own execution engine, tests and build, and is deployed at its own address. MAVILERA needs no textbook, course or account.
MAVILERA is a provisional project name, pending legal clearance.