MAVILERA SAP-2 Laboratory: documentation

Interactive Microprocessor Architecture Laboratory: Visualize. Execute. Understand.

About SAP-2

SAP-2 is the second of the simple-as-possible (SAP) computers, teaching designs by Albert Paul Malvino in his textbook Digital Computer Electronics (McGraw-Hill, first edition 1977; third edition with Jerald A. Brown, Glencoe/McGraw-Hill, 1993). The book presents SAP-1, SAP-2 and SAP-3 in turn as computers a student can build from digital components; its preface describes their instruction set as a subset of the Intel 8085's, and SAP-2's mnemonics, such as MVI, LDA, JNZ and CALL, are the 8085's. SAP-2 is a textbook design, not a commercial product.

SAP-2 has 64K of memory, the first 2K of it read-only, an accumulator and the registers B and C, the sign and zero flags, conditional jumps, a subroutine call and return, and four ports: a hexadecimal keyboard, a hexadecimal display and serial lines. Its instruction set is the 43 instructions of the book's tables.

Why it matters: SAP-2 adds what SAP-1 lacks to be programmed like a real microprocessor: decisions on flags, loops, subroutines and input and output. It bridges SAP-1 and the 8080/8085 family that the book goes on to teach.

The detailed description of SAP-2 is chapter 11 of the book. The book has no DOI.

• Digital Computer Electronics, third edition A. P. Malvino, J. A. Brown. Glencoe/McGraw-Hill, 1993. ISBN 0-02-800594-5. Chapter 11: SAP-2.

Getting started

1. Open the application. The editor holds a short example program; Templates in the toolbar offers others, each showing one idea, with a note at the top on what to try.
2. Press Assemble (Ctrl+Enter). The listing shows each instruction's bytes with its address; errors are underlined in the editor and explained in the console.
3. Press Step (F10) a few times. The current instruction is marked in the editor and the listing, and the registers, flags and ports change. Each OUT 03H also writes a line in the console.
4. Press Step back (Shift+F10) to undo a step, or Run (F5) to run to HLT or to a breakpoint.
5. Choose Bus at the top. The same program now runs one T state per step on the drawing of the computer.

The example program of a new session:

        MVI C,05H     ; C <- 5, the count
loop:   MOV A,C       ; A <- C
        OUT 03H       ; port 3 <- A: the display, and a console line
        DCR C         ; C <- C - 1; Z = 1 when it reaches 0
        JNZ loop      ; again until C is 0
        HLT           ; stop

A run starts at 0000H. Memory from 0000H to 07FFH is read-only: a store there stops the run with a message.

The workspace

The page is a workspace of panes, as in a code editor.

• Header: the views (Instructions, Bus); the View menu (show or hide panes, reset the layout); the theme; projector mode; full screen; the keyboard summary; Help.
• Toolbar: Assemble, Run/Pause, Step back, Step, Step over, Step out, Run to cursor, Reset, the speed, Templates and the File menu. Each control has a tooltip with its name and key.
• Editor: SAP-2 assembly, with completion of mnemonics and registers, help when you point at a word (operands, operation, bytes and T states), find, and breakpoints in the line numbers.
• Listing: each instruction with its address and bytes, in hexadecimal and binary; the tabs Data and Symbols show the data and the labels.
• Instruction inspector: the fields of the selected instruction (op code, byte or address), and a scratch line that turns one instruction into its bytes or bytes into their instruction without changing the program.
• Registers, call stack and counters: A, B, C, PC, the flags S and Z, and the ports; the innermost CALL; the counters of instructions and T states.
• Memory and console: the memory, the Ports tab (below), and the console with the assembler's messages and the lines of OUT 03H.

Drag a divider to resize panes; the sizes are kept in this browser for each view.

Assembly language

One instruction or directive per line, with an optional label (ending in :) and an optional comment (starting with ;). Mnemonics are not case-sensitive. Operands are separated by a comma, as in MVI A,05H.

What each instruction does is shown when you point at it in the editor; the full description of the computer is in the book listed under About SAP-2.

Ports and keyboard

The Ports tab of the memory pane is the computer's front panel.

Each input is kept with the instruction it was entered before: stepping back past it withdraws it, and a reload or a long run replays it there. Reset clears the inputs.

Running and debugging

• Breakpoints: click a line number in the editor or an address in the listing (B on a row).
• Watchpoints: tick a register's eye to stop when it is written; double-click a memory byte, or use Watch, to stop when that byte is written.
• Step back undoes one step at a time, back to the start of the run.
• Step over (F11) runs a CALL to its RET; Step out (Shift+F11) runs to the RET of the present subroutine; Run to cursor (Ctrl+F10) stops at the editor's line.
• The call stack shows the innermost CALL only: SAP-2 keeps one return address, at FFFEH and FFFFH, and a CALL inside a subroutine overwrites it. The assembler warns when a program places something there.
• A run that does not halt stops after a large number of instructions, with a message in the console.

The Bus view

The drawing shows the W bus and the units on it: controller-sequencer, instruction register, program counter, MAR, memory, MDR, input ports, flags, accumulator A, ALU, TMP, B, C and output ports, with TMP2, a unit the simulator adds. Each step is one clock, one T state.

• The unit that drives the bus, the registers that load from it and the asserted control signals are highlighted. The status line names the T state, the instruction and its address.
• Step instruction and Back instruction go to the first T state of the next instruction, or of this one.
• Select a control signal, at its unit or in the Microinstruction tab, to trace it. Enter on a drawn element opens its details.
• The tabs under the drawing: Microinstruction (the control signals of the present T state and what each does), Sequence (the T states of the instruction and their transfers), Waveforms (chosen signals over the clocks run so far; select a clock to go to it), the listing and the memory.

The microprogram of the Bus view is the simulator's own design. The book gives the units, the fetch states T1 to T3, the number of T states of each instruction and the flag test of a conditional jump; TMP2 and the constants FFFEH and FFFFH are the simulator's additions. An ALU instruction with B or C writes its result in T2 of the next fetch, when the bus is idle.

Exercises

File ▸ Exercise… lists practice exercises written for MAVILERA, each with a task and a starter program. Run the tests runs your program with each test's memory bytes and inputs and shows expected against actual. No solutions are included. A teacher's exercise file (JSON, with "arch": "sap-2") opens with File ▸ Open.

Files, sharing and exports

• Your work is kept in this browser: after a refresh or a closed tab, the program, its file name, the cursor, breakpoints, watchpoints and the step you had reached come back.
• File ▸ Copy share link puts the program, the view and its settings into a link. They travel in the part after #, which the browser never sends to a server.
• File ▸ Save program and settings… writes a .json file; File ▸ Open reads it back, and also .asm files.
• File ▸ Data in and out… loads bytes into memory before a run, and saves a memory range.

The run exports replay the program from reset to its halt; the session you are in is not changed.

Offline use and privacy

• After a first visit, the hosted application opens without a network connection.
• The single-file version, offered on the home page, is one .html file that opens from the local disk and makes no network request.
• No account, no tracking, no upload: programs, data files and exports never leave the browser.

Keyboard reference

Limits of the model

• The Bus view is a teaching model of the computer's bus and controller, on the simulator's own microprogram. A simulation shows what the model does; it is not evidence of how a hardware build behaves.
• T states are counted, not timed: there are no gate delays and no clock frequency.

Licence and notices

© 2026 Sajid Muhaimin Choudhury. MAVILERA and its content (drawings, help texts, this documentation, example programs and exercises) are licensed under the Apache License, Version 2.0. The names and the logo are not licensed as trademarks.

SAP-2 is described in Digital Computer Electronics by Albert Paul Malvino and Jerald A. Brown, © 1977, 1983 McGraw-Hill, Inc. and © 1983, 1993 Glencoe/McGraw-Hill. MAVILERA reproduces no text or figure of the book; its simulator, drawings, microprogram, help and programs are its own. It is not affiliated with or endorsed by the authors or the publisher. Intel is a trademark of Intel Corporation or its subsidiaries.