SAJID Lab

LOR Request

Wed, 01 Jan 2025 00:00:00 +0000

Foreword

Letter of recommendation is a necessity to advance in your career. It brings me utmost joy to see our students succeed in life, and is always a pleasure to give recommendation letter to potential applicants for job or higher studies.

Please remember that I can only address your accomplishments that I was actively involved in. Ask yourself if I would be the right person to judge your research aptitude and skills. I will try to give an honest and impartial assessment, so also ask yourself if my recommendation would help or hurt your chances of succeeding.

Note: If you enrolled in Masters in BUET, and have dropped out / have F grades in courses, that will also be mentioned in your LOR. We have to comment about the motivation of the student, so you can guess what the response of that question will be in such a case.

Criteria for Getting Recommendation

you MUST meet at least one of the following descriptions/criteria before you try to make an appointment with me for recommendation request.

You performed MSc/PhD research work under my supervision
Final year thesis/project completed under my supervision
Performed some kind of project work under my guidance/in collaboration that resulted in a peer-reveiewed publication
You successfully completed my graduate level course
You are a colleague / part-time faculty member who directly took any class with me
I taught a final-year lab course that you successfully completed, and demonstrated a honours project ¹
I served as a member in your MSc/PhD examination committee
I was an external examiner of your Final year thesis/project

** for serial number 6 and above, I will only give LORs to schools that have application deadline on or AFTER December 15th of the calendar year. Kindly refrain from requesting LORs for other schools**

¹ based on sessional course project alone, it is diffcult to judge your motivation. However, if a project from a theory/lab course was truly exceptional, and resulted in a publication with my approval, I will be happy to recommend you based on your capacity to perform original research/review. Only for final-year lab-course, if I was directly assigned to your section, AND you completed an honours project successfully in that course, I can recommend you based on your output and ability to solve complex Engineering Problem.

Simply taking an undergraduate theory course does not give the instructor sufficient capacity to judge the research aptitude of a student. As such, if you only interacted with me as a student in my theory course, unfortunately, I will not be in a position to recommend you.

If you are currently enrolled in BUET MSc program under my supervision, please consult with me before applying. Also, consider not adding me as a recommender if your research progress is unsatisfactory. For students enrolled under other faculty members, I will only recommend you only if your current supervisor recommends. You should attach a copy of the consent in the email, otherwise I will have to personally call and confirm with him/her before giving the LOR.

Sample question and answer that I need to do for a LOR

Each Letter of Recommendation form is different, and many a times, I have to manually type out responses, in addition to the formatted LOR that needs to be submitted. Almost all programs require likeart charts. Here is an example of a school’s LOR. I am expected to judge each student, whether they fall under the Categories: Outstanding (Top 2%), Very Good (Top 10%), Good (Top 25%), Average (Top 50%), Below Average (Lower 50%), Not Applicable or Not Known

Overall scholarly ability
Technical ability in the field
Potential as a researcher
Potential as a teacher
Intellectual ability/capacity
Analytical and problem-solving ability
Quantitative skills
Meticulousness/attention to detail
Thoroughness in completing tasks
Oral communication skills
Written communication skills
Listening skills
Interpersonal skills
Maturity/emotional intelligence
Judgment/common sense
Ability to work well with others
Motivation
Initiative
Perseverance
Creativity/originality
Self-reliance and independence in scholarly work
Flexibility
Leadership potential
Self-confidence
Responsibility
Integrity
Work ethic
Respect for authority
Time management skills
Ability to work under pressure

List of Eligible Students

For convenience, I am explicitly listing students who only did my only undergraduate class and would be eligible for LOR. Other students are requested not to send me an email.

16 Batch - EEE 416 A1 & A2 (Student ID 001-065)
17 Batch - EEE 416 A1 & A2 (Student ID 001-065)
18 Batch - EEE 416 A2 (Student ID 033-065)
19 Batch - 151-180 (advisee), EEE 416 (Student ID 001-33, 131-163)

Limit of LOR Request

For my direct thesis students (undergraduate, Masters or PhD) there is no upper limit to giving LORs. For other cases, the number of LOR will be limited to 5.

Waiver of Access

In order to receive a LOR from me, you must Waive the right to access to what I write. If you do not waive your access, I would also decline to recommend you. I believe you should only get my recommendation if you trust my judgement sufficiently. I will, however, tell you in person, if I cannot give you a positive recommendation.

If I find that the waiver is not done in an LOR form, I will copy paste the following text in the LOR form:

"The detailed policy of my LOR is elaborated in my website https://www.sajid.bd/resources/academic/lor/, and the candidate still chose the option of not waiving the right to access this report. Since the applicant did not waive the right to access this report, I hereby decline to give a Letter of Recommendation. "

Steps to Get LOR:

Firstly go above to to check if you are eligible to get a LOR from me. If not I might not respond to your email, or just decline to recommend you.
If you are eligible to get a LOR, Please download and fill up the with your information.
In a single email, please send the following documents:
- completed LOR_Request_Form.docx
- Your transcript (if CGPA mentioning is needed)
- Your CV (Preferrably in this format:

In the body of the email, please again write information of the form, upto point 4, and request for the Letter of Recommendation

_If you do not email me properly, I will simply copy and send the following text (keeping it here for my convenience, so that I can copy/paste it.) _

Reply template for ineligible students

Dear X,
Thank you very much for your email. If you could kindly go to my website and first check if you are eligible to receive an LOR from me. If you are eligible, please fill out the and send me the email again.
Thank you

Reply template for eligible students

Dear X,
Thank you very much for your email. If you could kindly go to my website and, please fill out the and send me the email again. I will confirm receipt of the email. Start adding my email after my confirmation.
Once you finish submitting all LORs, kindly email and let me know, again, and I will try to submit all of your LORs in one go. You do not need to send me a draft LOR, just the form is sufficient.
For students enrolled under other faculty members, I will only recommend you only if your current supervisor recommends. You should attach a copy of the consent in the email, otherwise I will have to personally call and confirm with him/her before giving the LOR.
Thank you

Once I give you consent to give LOR by replying to your email, you may put my official email address sajid(at)eee.buet.ac.bd in the application portal.
For convenience, please submit the LOR request of ALL the universities at once. It is much easier for me to finish the LOR submission process in one sitting.
If I forget to submit the LOR, please send me an email reminder 1 day before the deadline.

Poems

Mon, 01 Jan 0001 00:00:00 +0000

শান্তির সন্ধানে

তান্ত্রিক জগতটার তন্দ্রা ছিড়ে

শকুনীর হিংস্র চোখের ফাঁদ চিরে

বাধ ভাঙ্গার উল্লাসে ওঠো মেতে,

ঝঞ্ঝা মাতোয়ারা এ রক্তিম ধরণীতে।

অশান্ত ধরায় যত ভয়াল দানব,

খঞ্জরের শিঞ্জনে আজ শিহরিত মানব!

রক্তের হোলিতে মেতেছে জন্তু জানব-

পিঞ্জর ভেঙ্গে ছুটে যাও শান্তির ঝান্ডা নেড়ে।

রণাঙ্গনের কলরবে পরিশ্রান্ত এ ধরা

যুদ্ধের দামামা আর শুনতে চায়না তারা

সাদা পতাকা, সাদা পায়রা, হোক না উড্ডীন

পিশাচীর যত রক্তপিপাসা, হয়ে যেতে দাও লীন।

বাংলাদেশের সনেট

কত পাখি চিরকাল এসে গায় গান,

আর কত সবুজ এই বাংলাদেশ!

রূপের যেন তার নেই কোনও শেষ-

বাংলার রূপ করিল মন হরণ ।

উত্তরে তার এক ভংগিল পর্বত,

দক্ষিণে সাগরের জলের টলমল,

চারিদিকে শুধু গাঢ় সবুজের ঢল,

আর আছে খাল বিল নদী শতশত।

গ্রীষ্মে যে তার এক রুদ্র ভয়াল রূপ,

বর্ষা এসে ধোয়ায় তার দুই চরণ,

শরতে যে আছে স্নিগ্ধ কোমল স্বরূপ,

হেমন্তে তার অপূর্ব আশ্চর্জ খেয়াল,

শীতে তার লৌহতুল্য কঠিন গড়ন,

বসন্তে সে শোভাময়, সজীব সরস।

Hobbies

Mon, 01 Jan 0001 00:00:00 +0000

Photography

I used to be a photography enthusiast with my Nikon D5100. Now, mostly I would just use my iphone to capture photos. .

Music

I taught my self to play guitar and still trying to improve my skills. I try to tab different Bangla songs as I learn them and upload them online. |

Website Development

I also like to hack PHP and html files for web development. I had created the new version of the website with Joomla. , , are some of the websites that I made. My current website is based on .

Currently, I maintain the following web projects:

The website of the Department of EEE, BUET, made with GravCMS. I had to program 3-4 custom plugins for the website using PHP/CSS:

My father, Late Dr. Naiyyum Choudhury’s remembrance and his works are hosted here:

My brother-in-law, Dr. Shakil Farid’s website:

Organizing Microsoft Teams Assignment Submissions with PowerShell

Sun, 04 Oct 2026 00:00:00 +0000

Microsoft Teams makes collecting assignments convenient, but the folder structure obtained when the submissions are downloaded from SharePoint is not always convenient for offline marking or archiving.

A bulk download is organized primarily by student. Each student has a folder, each assignment appears as a subfolder, and the submitted file may be stored inside another folder such as Version 1.

For example:

416-2026\
├── 2100001 - Student Name\
│ ├── Assignment 1\
│ │ └── Version 1\
│ │ └── report.pdf
│ └── Assignment 2\
│ └── Version 1\
│ └── presentation.pptx
├── 2100002 - Another Student\
│ ├── Assignment 1\
│ │ └── Version 1\
│ │ └── final-report.pdf
│ └── Assignment 2\
│ └── Version 2\
│ └── slides.pptx
└── ...

This structure is useful when you want to see everything submitted by one student. However, it is cumbersome when you want to mark or review one assignment for the entire class.

A short PowerShell script can reorganize the downloaded files automatically into:

_ByAssignment\
├── Assignment 1\
│ ├── report_2100001_v1.pdf
│ ├── final-report_2100002_v1.pdf
│ └── ...
└── Assignment 2\
 ├── presentation_2100001_v1.pptx
 ├── slides_2100002_v2.pptx
 └── ...

The new filename keeps the original filename and adds:

the student ID, taken from the first seven characters of the student’s folder name; and
the submission version, such as v1, v2, etc.

The original downloaded files are left untouched.

1. Open the class Team in SharePoint

Open the relevant Class Team in Microsoft Teams.

Navigate to the Team’s files and choose Open in SharePoint. Depending on the Teams interface in use, the command may appear as View in SharePoint.

This opens the SharePoint site associated with the Team.

Note

This can also be done from the web browser version of Teams.

2. Open Site contents

Once the Team site opens in SharePoint, select Site contents.

Depending on the SharePoint layout, Site contents may be visible in the site navigation or accessible through the Settings menu.

The Site contents page lists the document libraries and other resources associated with the Team.

3. Open Student Work → Submitted Files

From Site contents, locate and open the document library named Student Work.

Inside Student Work, open Submitted Files.

The path is:

Site contents
 └── Student Work
 └── Submitted Files

Inside Submitted Files, the folders are normally organized student by student:

Submitted Files\
├── 2100001 - Student Name\
├── 2100002 - Student Name\
├── 2100003 - Student Name\
└── ...

Each student directory contains folders corresponding to that student’s assignments.

4. Download the submissions

Select the Submitted Files folder and choose Download.

SharePoint will prepare the selected contents for download, normally as a compressed archive.

Save the archive and extract it to a convenient local folder.

For example:

F:\416-2026

After extraction, the top level may look like:

F:\416-2026\
├── 2100001 - Student Name\
├── 2100002 - Student Name\
├── 2100003 - Student Name\
└── ...

A particular student submission might look like:

2100001 - Student Name\
└── EEE 416 - Project Report and Presentation Sli\
 └── Version 1\
 ├── EEE416-Jan2026-B1-G04-Final-Presentation-v9.pptx
 ├── EEE416_B1-04_Final_Project_presentation.pdf
 ├── EEE416_B1-04_Final_Project_Report (2) (1).docx
 └── EEE416_B1-04_Final_Project_Report.pdf

This is the structure that the PowerShell script will reorganize.

5. Create the PowerShell script

Open Notepad, Visual Studio Code, or another plain-text editor.

Create a file named:

Organize-Teams-Assignments.ps1

For example, save it in the downloaded course folder:

F:\416-2026\Organize-Teams-Assignments.ps1

Paste the following script into the file:

<#
.SYNOPSIS
 Reorganize downloaded Microsoft Teams / SharePoint
 student submissions by assignment.

.DESCRIPTION
 Expected source structure:

 SourceRoot\
 2100001 - Student Name\
 Assignment A\
 Version 1\
 file1.pdf
 file2.docx
 Assignment B\
 Version 2\
 file3.pptx

 Produces:

 SourceRoot\_ByAssignment\
 Assignment A\
 file1_2100001_v1.pdf
 file2_2100001_v1.docx
 Assignment B\
 file3_2100001_v2.pptx

 The student ID is taken from the first seven characters
 of the student folder name.

 The original files are copied, not moved.
#>

param(
 [string]$SourceRoot = "F:\416-2026",
 [string]$OutputRoot = "F:\416-2026\_ByAssignment"
)

$ErrorActionPreference = "Stop"


# ------------------------------------------------------------
# Generate a unique destination filename if necessary
# ------------------------------------------------------------
function Get-UniqueDestinationPath {
 param(
 [Parameter(Mandatory)]
 [string]$Path
 )

 if (-not (Test-Path -LiteralPath $Path)) {
 return $Path
 }

 $directory = [System.IO.Path]::GetDirectoryName($Path)
 $baseName = [System.IO.Path]::GetFileNameWithoutExtension($Path)
 $extension = [System.IO.Path]::GetExtension($Path)

 $counter = 2

 do {
 $candidate = Join-Path $directory (
 "{0}_{1}{2}" -f $baseName, $counter, $extension
 )

 $counter++
 }
 while (Test-Path -LiteralPath $candidate)

 return $candidate
}


# ------------------------------------------------------------
# Check source directory
# ------------------------------------------------------------
if (-not (Test-Path -LiteralPath $SourceRoot -PathType Container)) {
 throw "Source folder does not exist: $SourceRoot"
}


# ------------------------------------------------------------
# Create output directory
# ------------------------------------------------------------
New-Item `
 -ItemType Directory `
 -Path $OutputRoot `
 -Force |
 Out-Null


Write-Host ""
Write-Host "Source : $SourceRoot"
Write-Host "Output : $OutputRoot"
Write-Host ""

$CopiedCount = 0
$StudentCount = 0


# ------------------------------------------------------------
# Student directories are expected to begin with a
# seven-digit student ID.
#
# Example:
#
# 2100001 - Student Name
# ------------------------------------------------------------
$StudentFolders = Get-ChildItem `
 -LiteralPath $SourceRoot `
 -Directory |
 Where-Object {
 $_.FullName -ne $OutputRoot -and
 $_.Name -match '^\d{7}'
 }


foreach ($StudentFolder in $StudentFolders) {

 $StudentCount++

 $StudentID = $StudentFolder.Name.Substring(0, 7)

 Write-Host "Student: $StudentID [$($StudentFolder.Name)]" `
 -ForegroundColor Cyan


 # --------------------------------------------------------
 # Immediate subdirectories are treated as assignments
 # --------------------------------------------------------
 $AssignmentFolders = Get-ChildItem `
 -LiteralPath $StudentFolder.FullName `
 -Directory


 foreach ($AssignmentFolder in $AssignmentFolders) {

 $AssignmentName = $AssignmentFolder.Name

 $DestinationAssignmentFolder = Join-Path `
 $OutputRoot `
 $AssignmentName

 New-Item `
 -ItemType Directory `
 -Path $DestinationAssignmentFolder `
 -Force |
 Out-Null


 # Find all submitted files within the assignment
 $Files = Get-ChildItem `
 -LiteralPath $AssignmentFolder.FullName `
 -File `
 -Recurse


 foreach ($File in $Files) {

 # Default to version 1
 $Version = 1

 $CurrentDirectory = $File.Directory

 # Walk upwards looking for "Version N"
 while (
 $null -ne $CurrentDirectory -and
 $CurrentDirectory.FullName.StartsWith(
 $AssignmentFolder.FullName,
 [System.StringComparison]::OrdinalIgnoreCase
 )
 ) {

 if ($CurrentDirectory.Name -match '(?i)^Version\s*(\d+)$') {
 $Version = [int]$Matches[1]
 break
 }

 if ($CurrentDirectory.Name -match '(?i)^Version$') {
 $Version = 1
 break
 }

 if ($CurrentDirectory.FullName -eq $AssignmentFolder.FullName) {
 break
 }

 $CurrentDirectory = $CurrentDirectory.Parent
 }


 $OriginalBaseName =
 [System.IO.Path]::GetFileNameWithoutExtension($File.Name)

 $Extension = $File.Extension


 # New filename:
 #
 # OriginalName_StudentID_vN.ext
 #
 $NewFileName = "{0}_{1}_v{2}{3}" -f `
 $OriginalBaseName,
 $StudentID,
 $Version,
 $Extension


 $DestinationPath = Join-Path `
 $DestinationAssignmentFolder `
 $NewFileName


 # Prevent accidental overwriting
 $DestinationPath = Get-UniqueDestinationPath `
 -Path $DestinationPath


 Copy-Item `
 -LiteralPath $File.FullName `
 -Destination $DestinationPath


 $CopiedCount++


 Write-Host (
 " {0} -> {1}" -f
 $File.Name,
 [System.IO.Path]::GetFileName($DestinationPath)
 )
 }
 }
}


Write-Host ""
Write-Host "============================================" `
 -ForegroundColor Green

Write-Host "Processing complete." `
 -ForegroundColor Green

Write-Host "Students processed : $StudentCount"
Write-Host "Files copied : $CopiedCount"
Write-Host "Output folder : $OutputRoot"

Write-Host "============================================" `
 -ForegroundColor Green

6. Set the source and output folders

Near the beginning of the script are these lines:

[string]$SourceRoot = "F:\416-2026",
[string]$OutputRoot = "F:\416-2026\_ByAssignment"

Change F:\416-2026 to the directory where you extracted your own Teams submissions.

For example:

[string]$SourceRoot = "D:\Courses\EEE416\Submissions",
[string]$OutputRoot = "D:\Courses\EEE416\Submissions\_ByAssignment"

The _ByAssignment folder does not need to exist beforehand. The script creates it automatically.

7. Open PowerShell in the folder

Open the downloaded submissions folder in File Explorer.

One convenient method is:

Click the File Explorer address bar.
Type powershell.
Press Enter.

PowerShell will open with that folder as its current directory.

Alternatively, open PowerShell normally and change directories:

cd F:\416-2026

Confirm that the script is present:

dir

You should see:

Organize-Teams-Assignments.ps1

8. Run the script

Run:

.\Organize-Teams-Assignments.ps1

The script processes each student folder and displays its progress.

For example:

Student: 2100001 [2100001 - Student Name]

 EEE416-Jan2026-B1-G04-Final-Presentation-v9.pptx
 -> EEE416-Jan2026-B1-G04-Final-Presentation-v9_2100001_v1.pptx

 EEE416_B1-04_Final_Project_Report.pdf
 -> EEE416_B1-04_Final_Project_Report_2100001_v1.pdf

At the end, it displays a summary:

============================================
Processing complete.
Students processed : 52
Files copied : 187
Output folder : F:\416-2026\_ByAssignment
============================================

If PowerShell blocks the script

Some Windows systems may prevent .ps1 files from running because of the PowerShell execution policy.

To allow the script only for the current PowerShell session, run:

Set-ExecutionPolicy -Scope Process Bypass

Then run the script again:

.\Organize-Teams-Assignments.ps1

Closing that PowerShell window removes the temporary setting.

Warning

On computers managed by an organization, PowerShell execution policy may be centrally controlled. Follow your organization’s IT policy rather than changing a machine-wide execution policy.

The resulting folder structure

For this original submission:

2100001 - Student Name\
└── EEE 416 - Project Report and Presentation Sli\
 └── Version 1\
 ├── EEE416-Jan2026-B1-G04-Final-Presentation-v9.pptx
 ├── EEE416_B1-04_Final_Project_presentation.pdf
 ├── EEE416_B1-04_Final_Project_Report (2) (1).docx
 └── EEE416_B1-04_Final_Project_Report.pdf

the script creates:

_ByAssignment\
└── EEE 416 - Project Report and Presentation Sli\
 ├── EEE416-Jan2026-B1-G04-Final-Presentation-v9_2100001_v1.pptx
 ├── EEE416_B1-04_Final_Project_presentation_2100001_v1.pdf
 ├── EEE416_B1-04_Final_Project_Report (2) (1)_2100001_v1.docx
 └── EEE416_B1-04_Final_Project_Report_2100001_v1.pdf

A later submission version is labelled accordingly. For example:

2100002 - Student Name\
└── Project Report\
 └── Version 3\
 └── Final Report.pdf

becomes:

_ByAssignment\
└── Project Report\
 └── Final Report_2100002_v3.pdf

What the script does

Identifies the student

Only folders beginning with seven digits are treated as student folders:

2100001 - Student Name

The first seven characters become the student ID:

Creates one folder per assignment

The existing assignment folder names are reused automatically. There is no need to enter the assignment names separately.

Detects submission versions

Folders such as:

Version 1
Version 2
Version 3

are converted to filename suffixes:

_v1
_v2
_v3

If a file is not contained in a numbered Version folder, the script assumes version 1.

Keeps the original filename

The existing filename is retained. The student ID and submission version are inserted before the extension.

For example:

Project Report.pdf

becomes:

Project Report_2100001_v1.pdf

Keeps the original download unchanged

The script uses Copy-Item, not Move-Item.

The original SharePoint download therefore remains intact and can be retained as the untouched archive.

Prevents silent overwrites

If two files would produce exactly the same destination filename, the script does not silently replace the first file. It creates a unique filename by adding _2, _3, and so on.

Why reorganize submissions this way?

The original Teams/SharePoint directory structure effectively answers:

What did this particular student submit?

For marking and course administration, the more useful question is often:

What did everyone submit for this particular assignment?

An assignment-wise directory is convenient for:

grading reports;
reviewing presentations;
distributing submissions among multiple evaluators;
checking whether everyone submitted the required file type;
batch-opening PDF or Word files;
running automated processing over submissions;
comparing different submission versions;
archiving a completed course; and
keeping the student ID attached to a file even when it is copied elsewhere.

Before deleting anything from SharePoint

Treat this workflow as an export and reorganization process, not as an immediate replacement for the original Teams/SharePoint records.

A sensible sequence is:

Download the submissions.
Keep the original extracted download.
Run the PowerShell script.
Check the number of students and copied files.
Spot-check several assignments and submission versions.
Make any archival or SharePoint cleanup decisions only after verifying the backup.

For important course records, keeping an untouched copy of the original download is a useful precaution.

Complete workflow

Microsoft Teams
 ↓
Open/View in SharePoint
 ↓
Site contents
 ↓
Student Work
 ↓
Submitted Files
 ↓
Download
 ↓
Extract archive
 ↓
Run PowerShell script
 ↓
_ByAssignment
 ↓
One folder per assignment
with Student ID + submission version
in each filename

The result is a simple assignment-oriented archive that is much easier to review, mark, distribute, and preserve than the student-oriented structure produced by the raw SharePoint download.

References

EEE 6516 (October 2026)

Thu, 01 Oct 2026 00:00:00 +0000

First class will be held online

The first class of EEE 6516 (Week 1, Lecture 0: an introduction to quantum computing and the course) will be held online on Zoom.

Zoom link:

Course announcements: For the latest announcements, materials and submissions, please use the class Team in your Microsoft Teams account. If you have not been added to the class Team, please e-mail the course instructor.

In 2025 the Nobel Prize in Physics was awarded for showing that an electrical circuit (a superconducting chip with a Josephson junction) can behave as a single quantum object, with quantised energy levels and quantum tunnelling. Circuits of this kind are the ancestors of today’s superconducting qubits. Quantum computing is therefore not only a subject for physicists. Its hardest problems are electrical-engineering problems: microwave control and readout, cryogenic electronics, photonics, signal processing, coding theory and the security of communication systems.

This course builds quantum computing from what an EEE graduate already knows: linear algebra, phasors, signals, probability and digital logic. No background in quantum mechanics is assumed. Every idea is also tested in simulation, using free, open-source software that runs on your own laptop.

Course Information


Course	EEE 6516 – Quantum Computing (postgraduate)
Instructor	Dr. Sajid Muhaimin Choudhury, Professor, Department of EEE, BUET (SAJID Lab)
Office	EEE 222, ECE Building, BUET
E-mail
Classes	Tuesdays, two lectures of 75 minutes. Week 1 has one introductory class (online, see above); Week 7 has no lectures (midterm-assignment week); Week 13 is for final-project presentations
Communication	Microsoft Teams (materials, announcements, submissions, messages)

Syllabus

Course Content

Introduction to quantum computing; Postulates of quantum mechanics; Qubits and single-qubit gates; Operators and quantum measurement; Quantum information processing, superposition, entanglement, no cloning theorem, and quantum teleportation; Quantum circuits, controlled operation and measurement, universal quantum gates; Quantum algorithms: Deutsch-Jozsa algorithm, Grover’s algorithm, Shor’s algorithm, quantum Fourier transform and phase estimation; Density matrices and Bloch sphere representation of quantum variables; Quantum error correction and fault-tolerant architecture; Physical realization of quantum computers: harmonic oscillator, optical quantum computers, trapped ions, superconducting qubits, and new implementation schemes.

Prerequisites

Python, linear algebra and probability at the level of a BSc in EEE.
No quantum mechanics is assumed. Chapter 1 builds the mathematical toolkit (complex vectors, Dirac notation, operators and eigenvalues).

Course Outcomes (CO)

After completing this course, students will be able to:

CO No.	CO Statement	Domain and Taxonomy Level	Delivery Method(s)	Assessment Tool(s)
CO1	Apply the postulates of quantum mechanics and the linear algebra of qubits to compute states, gate actions, measurement probabilities and expectation values of single- and multi-qubit systems, including entangled and mixed states	C3: Cognitive / Apply	Lectures, handouts, worked examples, in-class activities	Class tests, term final
CO2	Analyse quantum algorithms (Deutsch–Jozsa, Bernstein–Vazirani, Grover, QFT, phase estimation, Shor), error-correcting codes and physical qubit platforms, and evaluate their resource costs and limitations against classical baselines and noise	C4: Cognitive / Analyse; C5: Cognitive / Evaluate	Lectures, handouts, simulations	Class tests, term final, midterm assignment
CO3	Implement, simulate and verify multi-qubit circuits and quantum dynamics with open-source simulators, including noise, interpret the results statistically, and communicate a reproducible simulation study	P4: Psychomotor / Mechanism; C6: Cognitive / Create (report)	Simulation exercises, live demonstrations, project supervision	Midterm assignment, final project (report, code, presentation)

Weekly Plan

Classes are on Tuesdays. Class tests are held outside lecture time.

Week	Lectures	Topics
1	0	Introduction to quantum computing and to the course (online)
2	1–2	Chapter 1: why quantum computing; complex vectors, Dirac notation, operators, eigenvalues
3	3–4	Chapter 2: states and measurement; single-qubit gates, Bloch sphere
4	5–6	Chapter 2: dynamics, observables, shot noise · Chapter 3: composite systems, two-qubit gates
5	7–8	Chapter 3: circuit model, universality; Qiskit, Cirq, PennyLane · Chapter 4: entanglement
6	9–10	Chapter 4: teleportation, superdense coding, CHSH · Chapter 5: oracles, Deutsch–Jozsa
7	—	No lectures: midterm-assignment week
8	11–12	Chapter 5: Grover search · Chapter 6: quantum Fourier transform
9	13–14	Chapter 6: phase estimation; order finding and Shor’s algorithm
10	15–16	Chapter 7: density matrices; quantum channels and noise
11	17–18	Chapter 8: error correction; stabilisers, surface code, fault tolerance
12	19–20	Chapter 9: superconducting qubits; trapped ions, photons, neutral atoms
13	—	Final-project presentations

Assessment

Grading Policy

Component	Weight	Notes
Class tests	15%	Three tests, 5% each, held outside lecture time
Midterm assignment	25%	Individual simulation study with a personal parameter set
Final project	30%	Groups of 2–3: reproduce and extend a published result by simulation; report, code and a 12-minute presentation
Term final	30%	As per the published routine

Assessment Milestones

Week	Milestone
5	CT1 (Chapters 1–2)
6	Midterm assignment released
7	Midterm assignment due (end of the week)
8	Final-project groups and paper proposal due
9	CT2 (Chapters 3–5)
11	CT3 (Chapters 6–7); final-project progress check
12	Final-project report and code due
13	Final-project presentations (12 minutes + Q&A)

Midterm Assignment and Final Project

Both are simulation projects.

Midterm assignment (individual). You implement a circuit or protocol from Chapters 2–5, predict its behaviour analytically, simulate it, and study one non-ideal effect such as noise. Each student receives a personal set of parameters.
Final project (groups of 2–3). Your group chooses a peer-reviewed paper whose central circuit or simulation fits on a laptop, either from the curated list or with the instructor’s approval at the proposal stage. You then:
1. reproduce one key figure or table;
2. extend it in one direction, for example noise level, problem size, a different simulator or error mitigation;
3. verify the results with analytic checks, fixed random seeds and stated tolerances.
Your code must regenerate every figure from a single command. Report templates (LaTeX, Overleaf-compatible) are provided on Teams.

Late Submission

Up to 2 days late: 10% penalty.
More than 2 days late: 25% penalty.

Policies

Incomplete Grade Policy

An I grade is given only if you have completed the midterm assignment and the final project (report and presentation), and miss the term final for reasons beyond your control. Apply to the Head of the Department of EEE within one week of the start of the final examinations. If you missed the assignment or the final project, you cannot receive an I grade, and you will be graded according to the grading policy. If you are unsure whether you can continue, please withdraw from the course.

Make-up Class Test Policy

A make-up class test is given only to students who missed a class test for circumstances beyond their control. It must be taken before the end of classes of the semester.

Academic Integrity and Generative AI

Plagiarism in a report or in code results in zero for that assessment. Reused code must be cited, including the paper’s own code if it is published. Copying another student’s or group’s code or results is plagiarism.
Generative AI: limited use. The analytic predictions, the design of your verification tests and the interpretation of your results must be your own work. Help with coding, debugging or language is allowed, but you must declare it in your report.
You must be able to explain every line of your code and every number in your report in the Q&A. Marks for a part can be withheld if you cannot explain it.

Textbooks and Resources

Course Materials

Chapter handouts and lecture slides for EEE 6516 (primary; on Teams).

Textbook

M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information, 10th anniversary edition, Cambridge University Press, 2010.

Software

All simulations run locally on your own laptop. No cloud account, token or paid service is needed.

Software	Version used in the course	Use
	—	First step: states and gates as arrays
+	2.5.2 / 0.17.2	Circuits, algorithms, noise models
	5.3.1	Density matrices, dynamics, hardware models
	1.7.0	Alternative circuit simulator (from Lecture 7)
	0.45.1	Alternative circuit simulator (from Lecture 7)
	1.16.0	Error-correction (stabiliser) simulation

Please install the course environment before Lecture 1, following Section 1.10 of the Chapter 1 handout.

Why Should an EEE Graduate Student Take This Course?

It is electrical engineering. A superconducting quantum computer is a microwave transmitter and receiver around a chip cooled to about 10–20 mK. Trapped-ion and neutral-atom machines are built from lasers, optics and detectors. Error correction combines coding theory with real-time decoding, and Shor’s algorithm has driven the move to new post-quantum cryptography standards (NIST FIPS 203, 204 and 205, published in August 2024).
EE and ECE departments teach it. For example:
- MIT 6.6410J Quantum Computation;
- Cornell ECE 5330 Quantum Physics and Engineering;
- Stony Brook ESE 512 Introduction to Quantum Systems Engineering;
- Purdue’s ECE Quantum Computing series.
It builds on the skills you have and adds new ones. You bring linear algebra, phasors, probability, digital logic, electromagnetics and Python. The course adds qubit calculations, the analysis of algorithms and hardware against classical baselines, and reproducible simulation. These open thesis directions in quantum devices, cryogenic microwave electronics, photonics, control and post-quantum security.

Course content follows the approved BUET syllabus for EEE 6516. Week-by-week topics may be adjusted during the term; announcements on Teams take precedence over this page.

OMRFlow

Wed, 23 Sep 2026 00:00:00 +0000

Motivation

Marking multiple-choice examinations by hand is slow, and the commercial OMR systems that automate it are closed, licence-bound and generally expect the answer sheets to be uploaded somewhere. A department that wants to keep student scripts on its own machines needs something it can run locally and inspect.

What it does

OMRFlow covers the sequence end to end: a template designer defines the registration markers and bubble grid for a sheet; scans are geometrically normalised for rotation, translation, scale, skew and perspective; recognition reports what it found, including blanks, multiple marks and uncertain reads rather than silently guessing; batches are processed across multiple cores and can resume after an interruption; a human resolves the uncertain cases, with an audit trail of every correction; attendance is reconciled; per-set answer keys are applied and verified; and reports are generated while preserving the custom formatting of the destination workbook.

Processing is local. The software is MIT-licensed and the source is on GitHub.

Status

Alpha. The current installable release is 0.1.0-alpha.1, published for evaluation and testing. The repository states that real-data qualification is not complete and that generated results should be independently verified before operational use. The repository is the place to check the current qualification status before relying on it for an examination.

Instructions to Hardware: A Gentle Introduction to Computer Architecture, ARM Assembly, and Verilog

Tue, 11 Aug 2026 00:00:00 +0000

This handout is designed to be followed from top to bottom during the workshop and reused later as a laboratory reference. The presentation is the primary source for the sequence, terminology, examples, and commands. Where the software-installation details were checked against current online documentation, those items are marked as web-verified and linked to official project or vendor pages.

Workshop question: How does a statement such as z = x + y; become an electrical operation inside a processor?

1. Workshop Overview

The workshop connects five views of the same computation:

C source
 ↓
ARM assembly
 ↓
32-bit machine code
 ↓
single-cycle datapath
 ↓
Verilog/SystemVerilog model + simulation waveform

The emphasis is not memorizing ARM encoding or HDL syntax. The goal is to see how software-visible instructions map onto registers, an ALU, memories, control logic, and observable digital signals.

The presentation introduces the layers in this order: source code, ARM assembly, machine code, instruction fields, a simplified processor, Verilog/SystemVerilog, testbenches, Icarus Verilog, and GTKWave. This handout keeps that teaching progression but moves the simple_sum.s → memfile.dat generation immediately before the full-processor simulation so that the laboratory workflow is executable from start to finish.

Suggested live-workshop use: follow the numbered hands-on procedures. Explanatory subsections can be read in more detail after the workshop.

2. Learning Objectives and Scope

By the end of the workshop, you should be able to:

explain the path C → assembly → machine code → datapath → HDL simulation;
recognize the roles of basic AArch32 registers such as r0, r1, r2, sp, lr, and pc;
explain the load–operate–store mental model;
generate A32 assembly using arm-none-eabi-gcc;
inspect machine-code words with arm-none-eabi-objdump;
describe and simulate a small combinational ALU;
distinguish a design module from a simulation testbench;
compile the supplied single-cycle processor and its separate testbench using Icarus Verilog;
change simulation length using +CYCLES=N without recompiling;
inspect the ARM execution in GTKWave and identify the successful final store.

This is deliberately a gentle introduction. The workshop does not attempt to cover pipelines, hazards, caches, speculative execution, virtual memory, detailed ABI rules, synthesis, place-and-route, or timing closure. Real Arm processors are much more sophisticated than the educational single-cycle model used here.

3. Required Software

Recommended platform: Windows 10/11, 64-bit, using the MSYS2 UCRT64 terminal. The presentation uses this Windows-native setup to avoid switching between Windows and WSL during a short laboratory session. MSYS2 documents UCRT64 as its modern Universal C Runtime environment and made it the default over MINGW64; the current package pages provide all tools used here.

3.1 Software and official pages

Software	Purpose in this workshop	Official page	Recommended installation
MSYS2	UCRT64 terminal and `pacman` package manager	/	Current 64-bit installer; open MSYS2 UCRT64
Native GCC	General C compiler used in the workshop toolchain		UCRT64 package
Arm bare-metal GCC	Generates A32 assembly and assembles `simple_sum.s`		UCRT64 package
Icarus Verilog	Compiles Verilog/SystemVerilog designs and testbenches	/	UCRT64 package
GTKWave	Opens VCD waveform files	/	UCRT64 package

Web-verified on 2026-08-11: the MSYS2 repository listed Arm GCC 16.1.0-1, Icarus Verilog 13.0-2, and GTKWave 3.3.127-1 in UCRT64. Exact package versions can change; use the current MSYS2 packages rather than pinning these versions.

3.2 Install MSYS2

Download the current 64-bit installer from the .
Install to the default short path such as C:\msys64, unless your laboratory has a managed-software policy.
From the Windows Start menu, open MSYS2 UCRT64. Do not use the plain MSYS2 MSYS shell for these package commands.

3.3 Update the package database and installed packages

Run in MSYS2 UCRT64:

pacman -Syu

If MSYS2 asks you to close the terminal after updating core components, close all MSYS2 windows, reopen MSYS2 UCRT64, and run:

pacman -Syu

again.

3.4 Install the workshop packages

pacman -S --needed \
 mingw-w64-ucrt-x86_64-gcc \
 mingw-w64-ucrt-x86_64-arm-none-eabi-gcc \
 mingw-w64-ucrt-x86_64-iverilog \
 mingw-w64-ucrt-x86_64-gtkwave

The Arm GCC package also pulls in the corresponding Arm binutils, including arm-none-eabi-objdump. The Icarus package contains both iverilog and vvp.

3.5 Verify the installation

gcc --version
arm-none-eabi-gcc --version
arm-none-eabi-objdump --version
iverilog -V
vvp -V
gtkwave --version

Pass condition: each command prints version information rather than command not found.

3.6 Create a workshop folder

mkdir -p ~/workshop
cd ~/workshop
pwd

You may instead use another writable folder. The important rule for the processor simulation is that arm_single.sv, arm_single_tb.sv, and memfile.dat must be in the working folder when you run the simulation.

4. Workshop Files

Before beginning the processor simulation, download the three required processor files and place them in the same working folder.

4.1 Required processor files

File	Purpose	Download	Place it in
`arm_single.sv`	Single-cycle ARM processor plus instruction and data memories		`~/workshop`
`arm_single_tb.sv`	Separate simulation testbench containing clock/reset generation, `+CYCLES=N` control, self-checking, and waveform dumping		`~/workshop`
`memfile.dat`	ARM machine-code program loaded by the processor’s instruction memory	Generate it in Hands-on 3B (not provided as a download)	`~/workshop`

After downloading, your workshop directory should contain:

workshop/
├── arm_single.sv
├── arm_single_tb.sv
└── memfile.dat

4.2 Files students create or generate during the workshop

File	Purpose	Action
`add.c`	Tiny C function for compiler observation	Create during Hands-on 1
`add_armv7a.s`	Compiler-generated assembly	Generated by GCC
`simple_alu.v`	4-bit combinational ALU	Create during Hands-on 2
`tb_simple_alu.v`	ALU testbench	Create during Hands-on 2
`alu_sim`	Compiled Icarus simulation	Generated by `iverilog`
`alu.vcd`	ALU waveform	Generated by `vvp`
`simple_sum.s`	Deterministic A32 demo program	Create during Hands-on 3
`simple_sum.o`	Assembled object file	Generated by GCC
`memfile.dat`	One machine-code word per line for instruction memory	Generate from `simple_sum.o`
`arm_single.out`	Compiled processor simulation	Generated by `iverilog`
`arm_single.vcd`	Full processor waveform	Generated automatically by the revised testbench

Recovery aid: the reference copies are included so a student who loses time to an editing error can rejoin the workshop. The live exercise is more useful if you create the files yourself first.

5. Toolchain Overview

The tools play different roles:

C source ──arm-none-eabi-gcc──> ARM assembly

ARM .s ──arm-none-eabi-gcc -c──> object file
object file ──arm-none-eabi-objdump──> assembly + machine words

Verilog/SystemVerilog sources ──iverilog──> compiled simulation
compiled simulation ──vvp──> execution + VCD file
VCD file ──gtkwave──> waveform inspection

Why this matters: iverilog and vvp are separate steps. Icarus documentation describes iverilog as the compiler/driver and vvp as the runtime that executes the compiled simulation.

6. What Is an ARM Instruction?

An instruction is a compact command specifying an operation and its operands. Consider:

ADD r2, r0, r1

ADD is the mnemonic: what operation to perform.
r2 is the destination: where the result is written.
r0 and r1 are the source operands.

In A32 state, the instruction is represented by a 32-bit machine word. Assembly is written for humans; the processor fetches the encoded word.

The workshop deliberately requests A32/Arm-state output with:

-marm

rather than Thumb output.

Check yourself: Which token selects the ALU operation in ADD r2, r0, r1?
Answer: the mnemonic/opcode, ADD.

7. ARM Registers and Load/Store Architecture

AArch32 exposes registers r0 through r15. For this workshop, the most useful names are:

r0–r3: commonly used for early function arguments, temporaries, and return values under common AArch32 calling conventions;
r13 / sp: stack pointer;
r14 / lr: link register, commonly holding a return address;
r15 / pc: program counter.

The architecture defines registers and instructions. A calling convention defines how software uses registers during function calls.

7.1 Load → operate → store

ARM is presented here as a load/store architecture: arithmetic operates on register values, while LDR and STR move data between registers and memory.

LDR r0, [r4, #8] @ r0 <- memory[r4 + 8]
ADD r2, r0, r1 @ r2 <- r0 + r1
STR r2, [r4, #12] @ memory[r4 + 12] <- r2

The simple mental model is:

Load → operate → store

Do not worry about the full set of ARM addressing modes today. For the workshop, base register plus immediate offset is sufficient.

8. Hands-on 1 — Generate ARM Assembly from C

Estimated time from the presentation: about 10 minutes.

Objective

Compile a small C function to ARMv7-A A32 assembly and identify the function label, registers, arithmetic operation, and return sequence.

Procedure

In the MSYS2 UCRT64 terminal, make sure you are in your workshop folder:

cd ~/workshop

Create the file:

notepad.exe add.c

Enter exactly:

int add(int a, int b) {
 return a + b;
}

Save and close Notepad.
Generate unoptimized assembly:

arm-none-eabi-gcc -S \
 -march=armv7-a -marm -O0 \
 add.c -o add_armv7a.s

Display the assembly:

cat add_armv7a.s

Find four features:
1. the function label add:;
2. registers carrying or temporarily holding the two input values;
3. an add instruction or equivalent arithmetic operation;
4. the return sequence, commonly ending in bx lr.

Presentation consistency note: the teaching discussion in the deck explicitly explains the verbose -O0 case and then compares optimization. This handout therefore uses ASCII -O0 for the first run. Use -O1 in the comparison below.

What the options mean

Option	Meaning
`-S`	Stop after compilation and emit assembly source
`-march=armv7-a`	Target the ARMv7-A architecture
`-marm`	Generate A32/Arm-state instructions rather than Thumb
`-O0`	Disable optimization for a more direct compiler output
`-o add_armv7a.s`	Name the output file

9. Read the Generated Assembly

Compiler output is not guaranteed to match the slide line for line. GCC version, optimization, and compiler decisions can change register allocation, stack-frame construction, directives, and comments.

A trimmed semantic pattern may look like:

add:
 ... @ optional prologue / argument handling
 add r3, r2, r3 @ arithmetic
 mov r0, r3 @ place return value in r0
 ... @ optional epilogue
 bx lr @ return

Focus on meaning:

Inputs: the first two integer arguments commonly arrive in r0 and r1.
Computation: at -O0, the compiler may copy, spill, and reload values before the actual ADD.
Return: the result commonly ends in r0; bx lr returns to the caller.

Compare with optimization

Run:

arm-none-eabi-gcc -S \
 -march=armv7-a -marm -O1 \
 add.c -o add_armv7a_O1.s

cat add_armv7a_O1.s

Ask yourself:

Which instructions disappeared?
Is the observable C behavior unchanged?
Which lines are the actual arithmetic and which support function entry/exit?

Optional machine-code view

arm-none-eabi-gcc -c \
 -march=armv7-a -marm -O0 \
 add.c -o add_armv7a.o

arm-none-eabi-objdump -d add_armv7a.o

This links the human-readable assembly to encoded instructions without requiring you to hand-encode every field.

10. Machine Code and `memfile.dat`

The simplified processor does not read .s assembly source. Its instruction memory uses $readmemh to read machine-code words from memfile.dat when the simulation starts.

Each line is one 32-bit instruction represented by 8 hexadecimal digits:

Assembly Machine code
ADD R3, R1, R2 E0813002
STR R3, [R0, #248] E58030F8
B halt EAFFFFFE

The workflow used later is:

assembly source
 ↓
object file
 ↓
objdump
 ↓
machine-code words
 ↓
memfile.dat
 ↓
instruction memory

Why this matters: compiler-generated C assembly is excellent for learning. For the educational processor, however, a short handwritten .s file gives a deterministic instruction sequence that stays within the processor’s supported subset.

11. A Quick Look at A32 Instruction Fields

You do not need to memorize full ARM encoding. The presentation uses only enough decoding to connect a 32-bit word to the processor’s controller.

11.1 Condition field

Bits 31:28 are the condition field. In the workshop program, the instructions use condition code:

1110 = E = always execute

11.2 Main operation class

The simplified controller uses bits 27:26 to distinguish broad instruction classes:

00 data processing
01 memory access (LDR / STR)
10 branch

11.3 Example: `ADD R3, R1, R2`

E0813002

Important fields are:

condition = E / always;
operation class = data processing;
data-processing opcode = ADD;
Rn = R1;
Rd = R3;
register operand Rm = R2.

11.4 Memory and branch examples

LDR R1, [R0, #0] @ E5901000
STR R3, [R0, #248] @ E58030F8
B halt @ EAFFFFFE

The single-cycle processor does not implement an OUT or HLT instruction. The workshop models output as a store to a watched address and models halting as an infinite branch plus testbench-controlled $finish.

12. The Simplified ARM Processor

The supplied processor is an educational A32-compatible subset. Its decoder supports the instructions used in the presentation:

ADD
SUB
AND
ORR
LDR
STR
B

The source contains a controller, datapath, register file, ALU, immediate extender, multiplexers, PC logic, instruction memory, and data memory.

This is not a complete modern Arm core. Its purpose is to make instruction execution traceable.

The full demonstration program conceptually performs:

mem[0] = 3
mem[1] = 4

R1 = mem[0]
R2 = mem[1]
R3 = R1 + R2

store R3 to address 0xF8
branch forever

The data memory is not initialized from memfile.dat, so the program first writes 3 and 4 into mem[0] and mem[1] before loading them back.

13. The Single-Cycle Datapath

A microarchitecture is the hardware organization used to implement an architecture. In this teaching model, each instruction completes through the datapath in a single clock cycle.

For a register-to-register instruction such as:

ADD r2, r0, r1

trace the operation as follows:

Fetch: the PC selects a word in instruction memory.
Decode: instruction fields select r0, r1, and destination r2.
Read operands: the register file presents the current source values.
Execute: control selects the ADD function and the ALU computes the sum.
Write back: the ALU result is written to r2.

No data-memory access is needed for this register-to-register ADD.

Check yourself: Which major datapath block is present but bypassed for ADD r2, r0, r1?
Answer: data memory.

14. Verilog/SystemVerilog Essentials

Verilog describes hardware, not a sequential list of software commands. A module represents logic that exists concurrently.

Three ideas are sufficient for this workshop:

Module interface: inputs and outputs are signals crossing the hardware boundary.
Combinational behavior: always @(*) describes logic whose output responds to current inputs.
Testbench: a separate simulation-only module drives inputs, observes outputs, and can request waveform recording.

A combinational decision network can be written as:

always @(*) begin
 case (op)
 2'b00: y = a + b;
 // ...
 endcase
end

The full processor source uses SystemVerilog constructs such as logic, always_comb, and always_ff. Therefore the processor compile command uses:

-g2012

Icarus documents -g2012 as enabling the IEEE 1800-2012 SystemVerilog language level.

15. Hands-on 2A — Build the 4-bit ALU

Estimated time from the presentation: about 8 minutes.

Objective

Create a four-operation combinational ALU with two 4-bit inputs, a 2-bit operation selector, and a 4-bit result.

Operation table

`op`	Operation	Expression
`00`	ADD	`a + b`
`01`	SUB	`a - b`
`10`	AND	`a & b`
`11`	OR	`a \| b`

Because y is only four bits wide, arithmetic wraps modulo 16.

Procedure

Create the source file:

notepad.exe simple_alu.v

Enter:

module simple_alu(
 input [3:0] a,
 input [3:0] b,
 input [1:0] op,
 output reg [3:0] y
);

always @(*) begin
 case(op)
 2'b00: y = a + b;
 2'b01: y = a - b;
 2'b10: y = a & b;
 2'b11: y = a | b;
 endcase
end

endmodule

Save and close the file.

Before simulating, predict the outputs for:

a = 6
b = 3

16. Hands-on 2B — Test and Inspect the ALU

Create the testbench

Create:

notepad.exe tb_simple_alu.v

Enter:

module tb_simple_alu;

reg [3:0] a, b;
reg [1:0] op;
wire [3:0] y;

simple_alu uut (
 .a(a),
 .b(b),
 .op(op),
 .y(y)
);

initial begin
 $dumpfile("alu.vcd");
 $dumpvars(0, tb_simple_alu);

 a = 4'd6;
 b = 4'd3;

 op = 2'b00; #10;
 op = 2'b01; #10;
 op = 2'b10; #10;
 op = 2'b11; #10;

 $finish;
end

endmodule

Compile, simulate, inspect

Compile:

iverilog -o alu_sim simple_alu.v tb_simple_alu.v

Run:

vvp alu_sim

Confirm the waveform exists:

ls -l alu.vcd

Open GTKWave:

gtkwave alu.vcd

In GTKWave, select hierarchy tb_simple_alu, then add:

a
b
op
y

Zoom to the full 0–40 interval.

Expected behavior:

Time	`op`	Operation	`y` decimal	`y` binary
0–10	`00`	ADD	9	`1001`
10–20	`01`	SUB	3	`0011`
20–30	`10`	AND	2	`0010`
30–40	`11`	OR	7	`0111`

Engineering habit: predict → edit → compile → simulate → inspect → explain. A tool completing without error is not, by itself, proof that the design is correct.

17. Hands-on 3A — Write the Deterministic ARM Program

The C example was useful for observing the compiler, but the simplified processor supports only a small instruction subset. For a deterministic full-processor demonstration, write the exact assembly program used by the presentation.

Procedure

In ~/workshop, create:

notepad.exe simple_sum.s

Enter exactly:

.syntax unified
.arch armv7-a
.arm
.global _start

_start:
 SUB R0, R15, R15 @ R0 = 0
 ADD R1, R0, #3 @ R1 = 3
 STR R1, [R0, #0] @ mem[0] = 3

 ADD R2, R0, #4 @ R2 = 4
 STR R2, [R0, #4] @ mem[1] = 4

 LDR R1, [R0, #0] @ R1 = mem[0]
 LDR R2, [R0, #4] @ R2 = mem[1]
 ADD R3, R1, R2 @ R3 = R1 + R2 = 7

 STR R3, [R0, #248] @ write result to testbench output address
halt:
 B halt @ pseudo-HLT

What the program does

SUB R0, R15, R15 makes R0 = 0 and uses it as the base address.
The first two STR instructions initialize data-memory words 0 and 1.
The two LDR instructions read back 3 and 4.
ADD R3, R1, R2 produces 7.
The final STR writes 7 to byte address 248 = 0xF8.
B halt loops forever as a pseudo-halt.

Why initialize memory in software? The supplied dmem array is not loaded by $readmemh; only the instruction memory imem reads memfile.dat.

18. Hands-on 3B — Generate `memfile.dat`

Procedure

Assemble the handwritten program:

arm-none-eabi-gcc -c \
 -march=armv7-a -marm \
 simple_sum.s -o simple_sum.o

Inspect assembly and machine code side by side:

arm-none-eabi-objdump -d simple_sum.o

Export one machine-code word per line:

arm-none-eabi-objdump -d simple_sum.o | \
 awk '/^[[:space:]]*[0-9a-f]+:/ {print toupper($2)}' > memfile.dat

Inspect the result:

cat memfile.dat

Expected file:

E04F000F
E2801003
E5801000
E2802004
E5802004
E5901000
E5902004
E0813002
E58030F8
EAFFFFFE

Verify that the processor files and machine-code file are together:

ls -l arm_single.sv arm_single_tb.sv memfile.dat

Expected result: the last two lines are E58030F8 and EAFFFFFE.

19. Separated Processor and Testbench Architecture

The revised workshop workflow keeps the processor design and simulation scaffolding in separate files.

arm_single.sv
 processor + memories
 ├── top
 ├── arm
 │ ├── controller
 │ └── datapath
 ├── imem
 └── dmem

arm_single_tb.sv
 clock generation
 reset generation
 +CYCLES=N run-time control
 success self-check
 waveform dumping

memfile.dat
 ARM machine-code program

The exact supplied processor uses:

initial
 $readmemh("memfile.dat", RAM);

inside imem. The revised testbench already contains:

$dumpfile("arm_single.vcd");
$dumpvars(0, testbench);

Therefore do not manually add $dumpfile or $dumpvars to the processor source.

20. Hands-on 3C — Compile and Run the Processor

Procedure

Confirm the folder contains:

arm_single.sv
arm_single_tb.sv
memfile.dat

Compile both SystemVerilog files together:

iverilog -g2012 -Wall -s testbench \
 -o arm_single.out arm_single.sv arm_single_tb.sv

Run for 25 active processor cycles:

vvp arm_single.out +CYCLES=25

Observe the terminal messages. A successful run should report that the success condition was seen and then complete at the selected cycle limit.
Confirm the waveform was generated:

ls -l arm_single.vcd

Open it:

gtkwave arm_single.vcd

What the compile options mean

-g2012 — enable SystemVerilog 2012 syntax used by the source.
-Wall — enable a broad set of Icarus warnings.
-s testbench — select testbench as the top-level root module.
-o arm_single.out — name the compiled simulation.
both .sv files are listed because the design and testbench are separate.

Expected result: the testbench watches for a store of decimal 7 to byte address 0xF8. It records success but continues until the requested number of post-reset cycles has completed.

21. Runtime Cycle Control and Recompilation Rules

The revised testbench reads a plusarg at run time:

vvp arm_single.out +CYCLES=10
vvp arm_single.out +CYCLES=25
vvp arm_single.out +CYCLES=50
vvp arm_single.out +CYCLES=100

If the argument is omitted:

vvp arm_single.out

the testbench uses:

DEFAULT_CYCLES = 25

21.1 What `CYCLES` counts

CYCLES counts rising-edge processor cycles after reset is released.

The supplied testbench uses:

clock period = 10 ns
reset high for first 22 ns

The first active rising edge is therefore after the reset pulse has ended.

21.2 When to recompile

Recompile with iverilog when:

arm_single.sv changes;
arm_single_tb.sv changes.

Run again:

iverilog -g2012 -Wall -s testbench \
 -o arm_single.out arm_single.sv arm_single_tb.sv

Do not recompile when only +CYCLES=N changes. Simply rerun:

vvp arm_single.out +CYCLES=50

21.3 What if only `memfile.dat` changes?

You also do not need to recompile. $readmemh("memfile.dat", RAM) is executed when the simulation starts, so the next vvp run reads the current contents of memfile.dat.

Use:

vvp arm_single.out +CYCLES=25

again after regenerating memfile.dat.

22. GTKWave Inspection of the ARM Execution

Open:

gtkwave arm_single.vcd

22.1 Navigate the hierarchy

In the hierarchy pane, expand testbench.
Select dut for top-level processor-system signals.
Expand dut.arm and dut.arm.dp if you want deeper datapath signals.
Append the required traces to the waveform panel.

22.2 Recommended signals

Start with:

clk
reset
dut.PC
dut.Instr
dut.DataAdr
dut.WriteData
dut.MemWrite
dut.ReadData

The presentation also recommends useful internal signals where available:

dut.arm.ALUResult
dut.arm.dp.ReadData
dut.arm.dp.SrcA
dut.arm.dp.SrcB
dut.arm.dp.ALUResult

22.3 Change buses to hexadecimal

For 32-bit buses, hexadecimal is easier to compare with assembly and memfile.dat.

In GTKWave:

select a bus trace;
right-click;
choose Data Format → Hex.

GTKWave documentation supports displaying multi-bit vectors in bases including hexadecimal.

22.4 Zoom and follow the instruction stream

Use Zoom Full first. Then zoom around the final MemWrite pulse.

Look for:

reset starting high and then falling low;
PC progressing through byte addresses 0x00, 0x04, 0x08, …;
Instr matching the successive 32-bit words in memfile.dat;
store pulses on MemWrite;
ReadData showing 3 and 4 during the two LDR instructions;
the ALU result becoming 7 after ADD R3, R1, R2;
the final successful store.

23. Expected Processor Behaviour and Verification Checklist

The demonstration program is successful when this transaction appears:

MemWrite = 1
DataAdr = 0x000000F8
WriteData = 0x00000007

Why 0xF8?

word index = 62
byte address = 62 × 4 bytes
 = 248 decimal
 = 0xF8

The data memory uses:

RAM[a[31:2]]

so the external byte address 0xF8 selects internal word 62.

Verification checklist

reset begins high and then goes low.
PC starts at 0 after reset and normally advances by four bytes per instruction.
Instr follows the words in memfile.dat.
MemWrite pulses for STR R1,[R0,#0].
MemWrite pulses for STR R2,[R0,#4].
ReadData shows 0x00000003 during the first load.
ReadData shows 0x00000004 during the second load.
the ADD result reaches 0x00000007.
the final store has DataAdr = 0x000000F8.
the final store has WriteData = 0x00000007.
the testbench prints that the success condition was observed.
the B halt instruction causes repeated execution of the halt loop until the cycle limit ends the simulation.

Minimum useful GTKWave trace: clk, reset, PC, Instr, DataAdr/ALUResult, WriteData, MemWrite, and ReadData, with 32-bit buses displayed in hexadecimal.

24. Troubleshooting

`arm-none-eabi-gcc: command not found`

Check that you opened MSYS2 UCRT64, then install the Arm GCC package:

pacman -S mingw-w64-ucrt-x86_64-arm-none-eabi-gcc

Close and reopen UCRT64 if the path still has not refreshed.

`iverilog: command not found` or `vvp: command not found`

Install the Icarus UCRT64 package:

pacman -S mingw-w64-ucrt-x86_64-iverilog

The package includes both executables.

`Unable to open memfile.dat` / `$readmemh` error

The instruction memory opens memfile.dat using a relative path. Run vvp from the folder containing the file:

pwd
ls -l arm_single.sv arm_single_tb.sv memfile.dat

Then run:

vvp arm_single.out +CYCLES=25

File appears missing even though you saved it in Notepad

Windows may have saved a hidden .txt extension. Check:

ls -l

Look for names such as add.c.txt or simple_alu.v.txt.

Verilog syntax error in the ALU exercise

Check:

semicolons;
matching begin / end;
case / endcase;
module / endmodule;
straight ASCII quotation marks;
exact literal syntax such as 2'b00.

`arm_single.vcd` is not created

The revised testbench already contains the VCD dump statements. Check that:

arm_single_tb.sv was included in the compile command;
-s testbench selected the correct top module;
compilation succeeded;
you actually ran vvp arm_single.out ....

Do not add another $dumpfile or $dumpvars to arm_single.sv.

GTKWave opens but no traces are visible

Opening a VCD does not automatically append every signal to the wave panel. Select the appropriate hierarchy, select the signals, and use Append or Insert.

Bus values are hard to read

Change 32-bit buses to hexadecimal:

Right-click → Data Format → Hex

Unknown `x` values appear

Uninitialized registers or memory words can legitimately appear as x until they are written. In this processor, the data RAM is not pre-initialized. The demo program explicitly writes 3 and 4 before loading those locations.

If x values remain on values that should already have been initialized, verify the instruction sequence and the earlier write pulses.

The final value is wrong

Check in this order:

cat memfile.dat and compare it with the expected ten words;
verify simple_sum.s exactly matches the workshop program;
confirm the simulation ran long enough;
inspect PC and Instr to ensure the program is being fetched correctly;
inspect the two initialization stores;
inspect the two loads (ReadData = 3, then 4);
inspect the ADD result;
inspect the final MemWrite, DataAdr, and WriteData together.

The C-generated assembly differs from the handout

That is expected. Compiler version and optimization choices affect prologues, temporary registers, and exact instruction sequences. Identify the function label, addition, result placement, and return semantics rather than comparing every line.

Fast recovery sequence

pwd
ls -l
arm-none-eabi-gcc --version
arm-none-eabi-objdump --version
iverilog -V
vvp -V

25. Suggested Exercises and Extensions

These are deliberately small extensions. Keep the same workflow: predict → edit → compile → simulate → inspect → explain.

Exercise A — change the ALU inputs

Change:

a = 4'd9;
b = 4'd2;

Predict before simulating.

Expected values:

ADD = 11
SUB = 7
AND = 0
OR = 11

Explain 9 AND 2 bit by bit using:

1001
0010
----
0000

Exercise B — demonstrate XOR

A 2-bit selector already has only four encodings. For a minimal demonstration, temporarily replace AND:

2'b10: y = a ^ b;

A more complete extension would widen op and update the testbench.

Exercise C — add a zero flag

Add an output and drive it high whenever y is zero:

output zero;
assign zero = (y == 4'b0000);

Then update the testbench and inspect zero in GTKWave.

Exercise D — change only the processor run length

Without changing source files, compare:

vvp arm_single.out +CYCLES=10
vvp arm_single.out +CYCLES=25
vvp arm_single.out +CYCLES=50

Which run first contains the successful store? Why is recompilation unnecessary?

Exercise E — relate machine code to waveform

Pick one instruction from memfile.dat, find the same value on dut.Instr, and explain what changes in the datapath during that cycle.

Beyond this workshop

A natural curriculum path is:

ALU
 ↓
register file
 ↓
control decoder
 ↓
memory interface
 ↓
single-cycle processor
 ↓
instruction extension / FPGA project

The supplied educational processor is intentionally a stepping stone rather than an endpoint.

26. Summary and References

Three takeaways

Code becomes instructions. A compiler translates C into instructions encoded for a target architecture.
Datapaths execute instructions. Registers, ALU, memory interfaces, multiplexers, and control logic cooperate to change architectural state.
Verilog/SystemVerilog makes hardware observable. A design plus a testbench can be compiled, simulated, and inspected before hardware implementation.

Workshop and textbook reference

Sarah L. Harris and David Money Harris, Digital Design and Computer Architecture: ARM Edition, 1st ed., Morgan Kaufmann/Elsevier, 2015. The presentation uses Chapters 6–7 as its conceptual foundation.

Official technical references

Arm, ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, DDI 0406:
GCC, ARM target options:
GCC, overall compilation options including -S:
Icarus Verilog:
Icarus Verilog:
GTKWave:
MSYS2:
MSYS2:
MSYS2:
MSYS2 UCRT64 packages: , , ,

Hybrid Si--GST polarization-insensitive dynamically tunable bifocal metalens operating at a 1.55μm wavelength

Sat, 01 Aug 2026 00:00:00 +0000

Steane $[[7,1,3]]$ outer coding for loss-tolerant one-way quantum repeaters

Sat, 01 Aug 2026 00:00:00 +0000

Bangladeshi Currency Formatting and Amount-in-Words in Microsoft Excel

Tue, 24 Feb 2026 00:00:00 +0000

Bangladesh Crore–Lakh format · ৳ / BDT currency display · English and Bangla amount in words · No VBA

Microsoft Excel normally uses the international thousands–millions grouping system. It also does not provide a built-in function for converting a monetary amount into words.

For financial documents in Bangladesh, however, we often need numbers in forms such as:

৳ 1,99,66,612.24

and, in words:

One Crore Ninety-Nine Lakh Sixty-Six Thousand
Six Hundred and Twelve Taka and Twenty-Four Paisa Only

or in Bangla:

এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার
ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র

This guide shows how to do all three in Excel:

Format numbers using the Bangladeshi Crore–Lakh–Thousand grouping.
Add BDT or the ৳ Taka symbol without turning the number into text.
Convert an amount into words in English.
Convert an amount into words in Bangla.

Everything is done using Excel’s built-in formatting and worksheet formulas. No VBA, macros, or add-ins are required.

1. Format Numbers in Bangladeshi Crore–Lakh Style

Excel normally displays a large number using the international grouping convention:

99,999,999.99

In Bangladesh, the same number is normally written as:

9,99,99,999.99

The grouping is:

Crore | Lakh | Thousand | Units
 9 | 99 | 99 | 999.99

Excel can display this format while keeping the underlying cell as a normal numeric value.

Where to Paste the Custom Number Format

Select the cells containing the numbers.
Press Ctrl + 1.
Select the Number tab.
Select Custom from the Category list.
Click inside the Type box.
Delete the existing format shown there.
Paste the custom format given below.
Click OK.

For numbers with two decimal places, paste:

[>9999999]0","00","00","000.00;[>99999]#0","00","000.00;#,##0.00

For example:

99999999.99

will be displayed as:

9,99,99,999.99

Similarly:

12500000.50

will appear as:

1,25,00,000.50

and:

125000.75

will appear as:

1,25,000.75

The value stored in the cell is unchanged. Therefore, functions such as SUM, multiplication, division, sorting, filtering, and references to the cell continue to work normally.

Bangladeshi Number Format Without Decimal Places

If Paisa or decimal values are not required, use:

[>9999999]0","00","00","000;[>99999]#0","00","000;#,##0

For example:

99999999

will be displayed as:

9,99,99,999

2. Add the ৳ Taka Symbol or BDT

The same custom formatting technique can be used to add a currency identifier.

This allows Excel to display:

৳ 9,99,99,999.99

or:

BDT 9,99,99,999.99

while keeping the actual cell contents numeric.

Again, go to:

Ctrl + 1 → Number → Custom → Type

Display the ৳ Taka Symbol

Paste:

[>9999999]"৳ "0","00","00","000.00;[>99999]"৳ "#0","00","000.00;"৳ "#,##0.00

For example:

99999999.99

will display as:

৳ 9,99,99,999.99

The Bangladeshi Taka symbol is:

৳

You can copy the symbol directly from this page and paste it into Excel’s Custom Format box.

Display BDT Instead

If you prefer the currency abbreviation, use:

[>9999999]"BDT "0","00","00","000.00;[>99999]"BDT "#0","00","000.00;"BDT "#,##0.00

The same number will then appear as:

BDT 9,99,99,999.99

Taka Symbol Without Decimal Places

For whole-Taka values:

[>9999999]"৳ "0","00","00","000;[>99999]"৳ "#0","00","000;"৳ "#,##0

For example:

12500000

will display as:

৳ 1,25,00,000

BDT Without Decimal Places

Use:

[>9999999]"BDT "0","00","00","000;[>99999]"BDT "#0","00","000;"BDT "#,##0

which displays:

BDT 1,25,00,000

These formatting codes affect only how the value is displayed. They do not add text to the actual cell value.

3. Convert Taka and Paisa into Words in English

Excel does not have a built-in NUMBERTOWORDS() or equivalent currency function.

Modern versions of Excel, however, support LET and LAMBDA, which allow the entire conversion routine to be contained inside a single formula.

No Name Manager configuration or VBA code is required.

Requirements

You need a version of Excel that supports both:

LET
LAMBDA

A simple test for LAMBDA support is:

=LAMBDA(x,x)(1)

If Excel returns:

then LAMBDA is available.

English Amount-in-Words Formula

Suppose the amount is stored in cell:

A1

Paste the following formula into another cell:

=LET(
amount,A1,
wordTwo,LAMBDA(n,
 LET(
 x,INT(n),
 u,LAMBDA(k,CHOOSE(k+1,
 "Zero","One","Two","Three","Four","Five","Six","Seven","Eight","Nine",
 "Ten","Eleven","Twelve","Thirteen","Fourteen","Fifteen","Sixteen",
 "Seventeen","Eighteen","Nineteen")),
 tens,INT(x/10),
 ones,MOD(x,10),
 tt,IF(tens=2,"Twenty",
 IF(tens=3,"Thirty",
 IF(tens=4,"Forty",
 IF(tens=5,"Fifty",
 IF(tens=6,"Sixty",
 IF(tens=7,"Seventy",
 IF(tens=8,"Eighty",
 IF(tens=9,"Ninety","")))))))),
 IF(x<20,
 u(x),
 IF(ones=0,
 tt,
 tt&"-"&u(ones)
 )
 )
 )
),
wordThree,LAMBDA(n,
 LET(
 x,INT(n),
 h,INT(x/100),
 remainder,MOD(x,100),
 TRIM(
 IF(h=0,"",wordTwo(h)&" Hundred")&
 IF(AND(h>0,remainder>0)," and ","")&
 IF(remainder=0,"",wordTwo(remainder))
 )
 )
),
negativeAmount,amount<0,
totalPaisa,ROUND(ABS(amount)*100,0),
takaAmount,QUOTIENT(totalPaisa,100),
paisaAmount,MOD(totalPaisa,100),
croreAmount,INT(takaAmount/10000000),
remainderCrore,MOD(takaAmount,10000000),
lakhAmount,INT(remainderCrore/100000),
remainderLakh,MOD(remainderCrore,100000),
thousandAmount,INT(remainderLakh/1000),
balanceAmount,MOD(remainderLakh,1000),
takaText,TRIM(
 IF(croreAmount>0,wordThree(croreAmount)&" Crore ","")&
 IF(lakhAmount>0,wordThree(lakhAmount)&" Lakh ","")&
 IF(thousandAmount>0,wordThree(thousandAmount)&" Thousand ","")&
 IF(balanceAmount>0,wordThree(balanceAmount),"")
),
paisaText,IF(paisaAmount=0,""," and "&wordTwo(paisaAmount)&" Paisa"),
signText,IF(negativeAmount,"Minus ",""),
IF(
 takaAmount=0,
 signText&"Zero Taka"&IF(paisaAmount=0," Only",paisaText&" Only"),
 signText&takaText&" Taka"&IF(paisaAmount=0," Only",paisaText&" Only")
)
)

If your amount is stored somewhere else, simply change:

amount,A1,

For example, if the amount is in G13, use:

amount,G13,

The rest of the formula can remain unchanged.

English Examples

If A1 contains:

19966612.24

the formula returns:

One Crore Ninety-Nine Lakh Sixty-Six Thousand Six Hundred and Twelve Taka and Twenty-Four Paisa Only

Some additional examples:

Amount	Output
`100.00`	One Hundred Taka Only
`1250.00`	One Thousand Two Hundred and Fifty Taka Only
`55000.00`	Fifty-Five Thousand Taka Only
`125000.75`	One Lakh Twenty-Five Thousand Taka and Seventy-Five Paisa Only
`10000000`	One Crore Taka Only
`0.75`	Zero Taka and Seventy-Five Paisa Only
`-12.50`	Minus Twelve Taka and Fifty Paisa Only

Why `totalPaisa` Is Calculated First

The formula first converts the complete amount into Paisa:

totalPaisa,ROUND(ABS(amount)*100,0)

It then separates Taka and Paisa using:

takaAmount,QUOTIENT(totalPaisa,100)

and:

paisaAmount,MOD(totalPaisa,100)

This avoids floating-point rounding situations in which a value close to the next Taka could otherwise produce an invalid result such as:

100 Paisa

4. Convert Taka and Paisa into Words in Bangla

The same approach can be used to produce the complete amount in Bangla.

For example:

becomes:

পঞ্চান্ন হাজার টাকা মাত্র

and:

19966612.24

becomes:

এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র

The formula below contains the Bangla words for the numbers from 0 to 99 and then constructs hundreds, thousands, lakhs, and crores from them.

Bangla Amount-in-Words Formula

If the amount is stored in A1, paste:

=LET(
amount,A1,

wordTwo,LAMBDA(n,
 CHOOSE(INT(n)+1,
 "শূন্য",
 "এক",
 "দুই",
 "তিন",
 "চার",
 "পাঁচ",
 "ছয়",
 "সাত",
 "আট",
 "নয়",
 "দশ",
 "এগারো",
 "বারো",
 "তেরো",
 "চৌদ্দ",
 "পনেরো",
 "ষোল",
 "সতেরো",
 "আঠারো",
 "উনিশ",
 "বিশ",
 "একুশ",
 "বাইশ",
 "তেইশ",
 "চব্বিশ",
 "পঁচিশ",
 "ছাব্বিশ",
 "সাতাশ",
 "আটাশ",
 "ঊনত্রিশ",
 "ত্রিশ",
 "একত্রিশ",
 "বত্রিশ",
 "তেত্রিশ",
 "চৌত্রিশ",
 "পঁয়ত্রিশ",
 "ছত্রিশ",
 "সাঁইত্রিশ",
 "আটত্রিশ",
 "ঊনচল্লিশ",
 "চল্লিশ",
 "একচল্লিশ",
 "বিয়াল্লিশ",
 "তেতাল্লিশ",
 "চুয়াল্লিশ",
 "পঁয়তাল্লিশ",
 "ছেচল্লিশ",
 "সাতচল্লিশ",
 "আটচল্লিশ",
 "ঊনপঞ্চাশ",
 "পঞ্চাশ",
 "একান্ন",
 "বাহান্ন",
 "তিপ্পান্ন",
 "চুয়ান্ন",
 "পঞ্চান্ন",
 "ছাপ্পান্ন",
 "সাতান্ন",
 "আটান্ন",
 "ঊনষাট",
 "ষাট",
 "একষট্টি",
 "বাষট্টি",
 "তেষট্টি",
 "চৌষট্টি",
 "পঁয়ষট্টি",
 "ছেষট্টি",
 "সাতষট্টি",
 "আটষট্টি",
 "ঊনসত্তর",
 "সত্তর",
 "একাত্তর",
 "বাহাত্তর",
 "তিয়াত্তর",
 "চুয়াত্তর",
 "পঁচাত্তর",
 "ছিয়াত্তর",
 "সাতাত্তর",
 "আটাত্তর",
 "ঊনআশি",
 "আশি",
 "একাশি",
 "বিরাশি",
 "তিরাশি",
 "চুরাশি",
 "পঁচাশি",
 "ছিয়াশি",
 "সাতাশি",
 "আটাশি",
 "ঊননব্বই",
 "নব্বই",
 "একানব্বই",
 "বিরানব্বই",
 "তিরানব্বই",
 "চুরানব্বই",
 "পঁচানব্বই",
 "ছিয়ানব্বই",
 "সাতানব্বই",
 "আটানব্বই",
 "নিরানব্বই"
 )
),

wordThree,LAMBDA(n,
 LET(
 x,INT(n),
 hundreds,INT(x/100),
 remainder,MOD(x,100),

 hundredText,
 CHOOSE(hundreds+1,
 "",
 "একশ",
 "দুইশ",
 "তিনশ",
 "চারশ",
 "পাঁচশ",
 "ছয়শ",
 "সাতশ",
 "আটশ",
 "নয়শ"
 ),

 TRIM(
 hundredText&
 IF(AND(hundreds>0,remainder>0)," ","")&
 IF(remainder=0,"",wordTwo(remainder))
 )
 )
),

negativeAmount,amount<0,
totalPaisa,ROUND(ABS(amount)*100,0),

takaAmount,QUOTIENT(totalPaisa,100),
paisaAmount,MOD(totalPaisa,100),

croreAmount,INT(takaAmount/10000000),
remainderCrore,MOD(takaAmount,10000000),

lakhAmount,INT(remainderCrore/100000),
remainderLakh,MOD(remainderCrore,100000),

thousandAmount,INT(remainderLakh/1000),
balanceAmount,MOD(remainderLakh,1000),

takaText,TRIM(
 IF(croreAmount>0,wordThree(croreAmount)&" কোটি ","")&
 IF(lakhAmount>0,wordThree(lakhAmount)&" লাখ ","")&
 IF(thousandAmount>0,wordThree(thousandAmount)&" হাজার ","")&
 IF(balanceAmount>0,wordThree(balanceAmount),"")
),

paisaText,
IF(
 paisaAmount=0,
 "",
 " এবং "&wordTwo(paisaAmount)&" পয়সা"
),

signText,
IF(negativeAmount,"ঋণাত্মক ",""),

IF(
 takaAmount=0,
 signText&
 "শূন্য টাকা"&
 IF(
 paisaAmount=0,
 " মাত্র",
 paisaText&" মাত্র"
 ),

 signText&
 takaText&
 " টাকা"&
 IF(
 paisaAmount=0,
 " মাত্র",
 paisaText&" মাত্র"
 )
)
)

As with the English version, change:

amount,A1,

to the appropriate cell reference if necessary.

For example:

amount,G13,

Bangla Examples

Amount	Output
`100`	একশ টাকা মাত্র
`1250`	এক হাজার দুইশ পঞ্চাশ টাকা মাত্র
`55000`	পঞ্চান্ন হাজার টাকা মাত্র
`125000`	এক লাখ পঁচিশ হাজার টাকা মাত্র
`10000000`	এক কোটি টাকা মাত্র
`19966612.24`	এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র
`0.75`	শূন্য টাকা এবং পঁচাত্তর পয়সা মাত্র
`-1250.50`	ঋণাত্মক এক হাজার দুইশ পঞ্চাশ টাকা এবং পঞ্চাশ পয়সা মাত্র

The Bangla formula intentionally uses natural Bangla constructions.

For example:

is written as:

ছয়শ বারো

rather than attempting to translate the English phrase “Six Hundred and Twelve” literally.

Similarly:

55,000

becomes:

পঞ্চান্ন হাজার

5. Putting Everything Together

Suppose A1 contains:

19966612.24

Using the custom number format:

[>9999999]"৳ "0","00","00","000.00;[>99999]"৳ "#0","00","000.00;"৳ "#,##0.00

Excel displays the amount as:

৳ 1,99,66,612.24

The English formula can display:

One Crore Ninety-Nine Lakh Sixty-Six Thousand Six Hundred and Twelve Taka and Twenty-Four Paisa Only

while the Bangla formula can display:

এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র

A worksheet could therefore contain:

Amount:
৳ 1,99,66,612.24

Amount in Words:
One Crore Ninety-Nine Lakh Sixty-Six Thousand
Six Hundred and Twelve Taka and Twenty-Four Paisa Only

কথায়:
এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার
ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র

This is particularly useful for:

invoices,
bills,
payment certificates,
purchase orders,
budgets,
financial statements,
audit documents,
vouchers, and
other official financial records.

Formula Limits

The formulas in this post use the following Bangladeshi units:

Crore
Lakh
Thousand
Hundred
Taka
Paisa

The Crore component is handled as a value from 1 to 999. Therefore, the formulas are intended for amounts below:

1,000 Crore

or:

10,00,00,00,000 Taka

For typical invoices, budgets, accounting documents, and institutional financial records, this range is generally more than sufficient.

If still larger values are required, the formulas can be extended with units such as Arab and Kharab.

A Note on Bangla Number Spellings

Some Bangla number words have more than one spelling in common usage.

The Bangla formula above uses one consistent set of spellings. Because all words from 0 to 99 appear explicitly inside the CHOOSE() function, individual spellings can easily be changed if a particular institutional or editorial convention is preferred.

For example, changing one entry in the list changes that spelling everywhere the formula is used.

Conclusion

Excel can be adapted quite effectively for Bangladeshi financial documents without using VBA.

With Custom Number Formats, a value such as:

19966612.24

can be displayed as:

৳ 1,99,66,612.24

while remaining a normal numeric value that can still be used in calculations.

Using LET and LAMBDA, the same value can also be converted directly into English:

One Crore Ninety-Nine Lakh Sixty-Six Thousand Six Hundred and Twelve Taka and Twenty-Four Paisa Only

or Bangla:

এক কোটি নিরানব্বই লাখ ছেষট্টি হাজার ছয়শ বারো টাকা এবং চব্বিশ পয়সা মাত্র

The entire solution is formula-based and requires no VBA, macros, or external add-ins.

This post was written with assistance from ChatGPT.

Getting Citation Count - From Publish or Perish to TamperMonkey

Sat, 24 Jan 2026 00:00:00 +0000

Background

When I was in grad school, my PI frequently requested me to update their CVs - be that for new grant application, or be that for the annual vita update. I learned a new thing from them - including google scholar citation count in each article in their publication list. The work was unnecessarily tedious, and I found the tool Publish or Perish (PoP) from Harzing to be quite liberating. When I made my new website, I wrote some scripts that would quickly use the command line tool of PoP, and query the citation count. Unfortunately, Google scholar is now becoming unusable without logging into the account or solving captcha, which PoP is not supporting. Therefore, a new tool is needed for my workflow.

What I want

Since PoP was directly in my workflow, I want to produce a Publish and Perish style CSV, that would be used by my other python scripts to update my publication bib file. It would have been prohibitively timeconsuming in the past. Thankfully, I was familiar with a Chrome / Edge extension called TamperMonkey that would quickly run a JS file on top of the loaded Google Scholar profile. And vibe coding with ChatGPT gave me a working plugin within 30 minutes.

The plugin

I hosted the plugin in . Once you install tampermonkey, you need to run Edge in developer mode. Then you can download the PopCites csv and update your CV.

Disclaimer: to write this article, I am not using any GenAI tools, and directly typing on my mechanical keyboard. The words, grammatical mistakes etc are my own. I must confess, I heavily use GenAI myself, but feel like my own voice needs to be saved. Starting from this blog, I will explicitly mention if the article is written by AI or if it is my own work.

Scholar Profile Exporter

Sat, 24 Jan 2026 00:00:00 +0000

Motivation

Keeping per-article citation counts in a CV or publication list is tedious to do by hand. The Publish or Perish desktop tool used to fill that role, but Google Scholar increasingly requires a signed-in session or a CAPTCHA, which that tool does not handle.

What it does

The script runs as a TamperMonkey userscript on top of a loaded Google Scholar profile page — so it works within an ordinary signed-in browser session — and exports the profile in a Publish-or-Perish-style CSV, together with BibTeX links. That CSV is the input format an existing set of scripts already expects, so the downstream publication-list and BibTeX update workflow is unchanged.

Status

Active. Source is on GitHub; it requires the TamperMonkey browser extension.

EEE 415 (Jan 2026)

Thu, 01 Jan 2026 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team “EEE 415 C (July 2023)”.

Introduction

The syllabus of this course has been changed and the course has been completely redesigned from grounds up.

Syllabus (as approved in 2022)

Fundamentals of microprocessor and computer design, processor data path, architecture, microarchitecture, complexity, metrics, and benchmark; Instruction Set Architecture, introduction to CISC and RISC, Instruction-Level Parallelism, pipelining, pipelining hazards and data dependency, branch prediction, exceptions and limits, super-pipelined vs superscalar processing; Memory hierarchy and management, Direct Memory Access, Translation Lookaside Buffer; cache, cache policies, multi-level cache, cache performance; Multicore computing, message passing, shared memory, cache-coherence protocol, memory consistency, paging, Vector Processor, Graphics Processing Unit, IP Blocks, Single Instruction Multiple Data and SoC with microprocessors. Simple Arm/RISC-V based processor design with VerilogHDL

Introduction to embedded systems design, software concurrency and Realtime Operating Systems, Arm Cortex M / RISC-V microcontroller architecture, registers and I/O, memory map and instruction sets, endianness and image, Assembly language programming of Arm Cortex M / RISC-V based embedded microprocessors (jump, call-return, stack, push and pop, shift, rotate, logic instructions, port operations, serial communication and interfacing), system clock, exceptions and interrupt handling, timing analysis of interrupts, general purpose digital interfacing, analog interfacing, timers: PWM, real-time clock, serial communication, SPI, I2C, UART protocols, Embedded Systems for Internet of Things (IoT)

Grading Policy

Class Attendance (10%) – Class participation and attendance will be recorded in every class. 30 Marks as per university AC policy
Continuous Assessment (20%) – 1 assignment (20) – Mandatory 3 Class tests, best 2 counted (40)
Final Examination (70%)– A comprehensive term final examination will be held at the end of the Term following the guideline of the Academic Council

Weekly Schedule

As per the routine published in the Department of EEE website.

Textbooks

[Harris] Sarah Harris, David Harris – “Digital Design and Computer Architecture, ARM Edition, Morgan Kaufmann (2015) - Chapter 6,7,8

[Patterson] David A. Patterson and John L. Hennessy, “Computer Organization and Design – The Hardware / Software Interface ARM edition” Morgan Kaufmann - Chapter 1

[Zhu] Yifeng Zhu “Embedded Systems with ARM Cortex-M Microcontrollers with Assembly Language and C”

Semester Plan

Week	Lectures	Topic	Textbook
1	1-3	Fundamentals of microprocessor and computer design, processor data path, architecture, microarchitecture, introduction to CISC and RISC, complexity, metrics, and benchmark.	Patterson 1
2	4-6	Assembly Language.	Harris 6.1-6.3
3	7-9	Assembly Language Programming.	Harris 6.3
4	10-12	Machine Language, Compiling, Assembling.	Harris 6.4
5	13-15	Performance Analysis, Single Cycle and Multicycle Processor.	Harris 7.1-7.4
6	16-18	Pipelining, Hazards, Advanced Microarchitecture.	Harris 7.5,7.7
7	19-21	Memory Systems – Cache and Virtual Memory.	Harris 8.2-8.4
8	20-24	Introducing Embedded System Design, IoT, Arm Cortex m4.	Lecture Slides
9	25-27	General Purpose Input Output.	Zhu 14
10	28-30	General Purpose Timers.	Zhu 15.1-15.3
11	31-33	Interrupts.	Zhu 11, 15.4
12	34-36	ADC + DAC.	Zhu 20,21
13	37-39	Serial Communication.	Zhu 22

EEE 416 (Jan 2026)

Thu, 01 Jan 2026 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team.

2023Introduction

In the 2023 syllabus the 416 course will be heavily project focused. We will use the project of EEE 416 as a primary replacement of the Capstone Project, for culmination of program outcomes.

Syllabus

EEE 416

The sessional courses will be conducted in two parts. In the first part of the sessional course, the students will perform experiments in relevance with the EEE 415 course. In the second part of the course, the students will perform design projects to achieve specific program outcomes.

EEE 415

Course Objectives

To perform experiments in relevance with the theoretical concepts of the course EEE 415: Microprocessor and Embedded Systems
To conduct design projects in order achieve specific program outcomes described in the Course Outline

Course Outcomes

Upon successful completion of the course, students will be able to

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Utilize VerilogHDL, ARM assembly, C programming and microcontrollers boards for implementing and analyzing theoretical concepts at software and hardware levels	PO(e)	P4, C4	–	Lab Performance, Lab Test, Quiz, Viva, Project
CO2	Design an embedded system with appropriate considerations to safety, cultural, societal, and environmental considerations	PO(c)	C6	–	Project Report and Hardware demonstration
CO3	Assess impact of embedded systems project design on Societal, Health, Safety, Legal and Cultural Issues	PO(f)	C5	–	Presentation and Report
CO4	Evaluate Sustainability the and Impact of the Designed embedded systems Project in the Societal and Environmental Contexts	PO(g)	C5	–	Presentation and Report
CO5	Demonstrate membership and leadership in designing embedded system related problem solving	PO(i)	P7	–	Project logbook , Peer assessment, Viva, Presentation
CO6	Communicate effectively on embedded system related design with presentation and detailed report	PO(j)	A2	–	Video Presentation, Design Report
CO7	Demonstrate project management and cost analysis for embedded system project	PO(k)	A3	–	Project Report and Presentation

_ * Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation, PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work, PO(j). Communication, PO(k) Project management and finance, PO(l) Life-long Learning

For details of program outcome (PO) statements, please see the departmental website or course curriculum _

KPA Mapping

Weekly Plan

Week	Mode	Topic
1	Experiment 00	Introduction to Lab, Lab Policies and Tools
2	Experiment 01	Arm Cortex M: GPIO: Interfacing LED, Push-Button and Stepper Motor	CO1 (PO(e))
3	Experiment 02	Arm Cortex M: Interrupt and Timers I	CO1 (PO(e))
4	Experiment 03	Arm Cortex M: Interrupt and Timers II	CO1 (PO(e))
5	Presentation	· Project Proposal Presentation · Describe specific technical requirements to be attained during the project · Describe sustainability and impact of the work in societal and environmental contexts	CO4 (PO(g))
6	Experiment 04	Arm Cortex M: Analog Interfacing	CO1 (PO(e))
7	Experiment 05	Arm Assembly Language and Architecture	CO1 (PO(e))
8	Experiment 06	Arm Micro Architecture: Single Cycle, Multi Cycle and Pipelining	CO1 (PO(e))
9	Project Progress Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-1 · Present/demonstrate the technical progress of the project · Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project	CO2 (PO(c)) CO4 (PO(f))
10	Assessment	Lab Test	CO1 (PO(e))
12	Lab Quiz and Viva	Sessional Quiz	CO1 (PO(e)) CO2 (PO(c))
11	Project Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-2 · Present/demonstrate the technical progress of the project · Describe multidisciplinary aspects of the project · Describe how each team member has been effectively working (individually and as a member or leader) to attain the goals (Self- and peer-assessment of students)	CO5 (PO(c) CO7 (PO(i))
13	Final Presentation	· Describe how engineering management principles and economic decision-making applied to the project · Use multimedia and necessary documentation (user manual, video demonstration and project report) to clearly communicate the project	CO7 (PO(k)) CO6 (PO(j))
14	Project Demonstration	· Practical demonstration of the project: show evidence that specific technical requirements have been attained by the project	CO2 (PO(c))

Distribution of Marks

Class Participation and Attendance 10%
Lab Reports 5%
Lab Experiments 10%
Lab Test 15%
Sessional Quiz 15%
Final Project 45%
Total 100%

Lab Usage Policy

No Food or Drink is allowed in the laboratory.
At the beginning of each lab, please check out the “Embedded Systems Kit” box from Mr. Selim, writing your name and information in logbook. Please check individually if each component is in the box.
Report any missing parts at the beginning of the lab.
You will be financially responsible for unreported missing items
Do not separate / tear the jumper cable collection.
Before connecting the USB port, double check the power and ground connection of your externally connected components.

Exploiting Steane-Code Syndrome Redundancy in Hybrid Photonic–Stabilizer One-Way Repeaters

Thu, 01 Jan 2026 00:00:00 +0000

HBT Perovskite/CdS Solar Cell Reaching Efficiency Over 35% Using Periodic Triangular Gratings

Thu, 01 Jan 2026 00:00:00 +0000

Pi Web Kiosk

Wed, 24 Sep 2025 00:00:00 +0000

Motivation

A lobby display has to keep showing something sensible when nobody is watching it: when the network drops, when the site it mirrors is down, when the machine has been running for a fortnight, and outside the hours anyone is there to see it. Doing that reliably on a Raspberry Pi is mostly a matter of configuration rather than code, so the whole system is driven from a JSON file.

What it does

Two Chromium kiosk windows are placed across an extended dual-display desktop. Content is mirrored to an offline cache at setup, and the kiosk falls back to that cache automatically when the network or the live site is unavailable, switching back to the live URL once connectivity returns. A hard refresh runs every few hours, the machine reboots daily at a configurable time, and display hours, active weekdays and holiday handling are all set in the same configuration file. Startup and recovery are handled by systemd.

Status

Active, and in use: the README records that the kiosk runs the information display in the main lobby of the Department of Electrical and Electronic Engineering, BUET. MIT-licensed, with the setup script and systemd unit in the repository.

Puja Das Defends MSc Thesis

Wed, 24 Sep 2025 00:00:00 +0000

Congratulations to Puja Das for defending MSc. Thesis Titled “Efficiency Enhancement of HTL-Free Perovskite/Cadmium-Sulfide Heterojunction Solar Cell Incorporating Light Trapping Structure”.

Ayon Sarker Defends MSc Thesis

Sat, 05 Jul 2025 00:00:00 +0000

Congratulations to Ayon Sarker for defending MSc. Thesis Titled “DESIGN OF DUAL-BAND PLASMONIC ABSORBER FOR BIOMEDICAL SENSING AND ENVIRONMENTAL MONITORING”.

EEE 303 (Jul 2025)

Sun, 01 Jun 2025 00:00:00 +0000

Course announcements: For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Course Outcomes

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits	PO(a)	C4	Lectures, Homework	Class test, Final exam
CO2	identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits using Verilog, FPGA and PCB design tools	PO(e)	C2	Lectures, Homework	Class test, Final exam
CO3	design combinational and sequential logic circuits with practical constraints using Verilog	PO(c)	C6	Lectures, Tutorials, Homework	Assignment Class test, Final exam

CO No.

CO Statement

Corresponding PO(s)*

Domains and Taxonomy level(s)**

Delivery Method(s) and Activity(-ies)

Assessment Tool(s)

CO1

Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits

PO(a)

Lectures, Homework

Class test, Final exam

CO2

identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits using Verilog, FPGA and PCB design tools

PO(e)

Lectures, Homework

Class test, Final exam

CO3

design combinational and sequential logic circuits with practical constraints using Verilog

PO(c)

Lectures, Tutorials, Homework

Assignment

Class test, Final exam

Textbooks

[Harris] Digital Design and Computer Architecture ARM Edition
[Brown] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design” 3rd Edition, McGraw Hill (2014)
[Floyd] Thomas L. Floyd, “Digital Fundamentals” 11th Edition, Pearson (2015)
[Mano] Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL” 5th Edition, Pearson (2013)
[Malvino] Albert P. Malvino, Jerald A. Brown - Digital Computer Electronics-McGraw-Hill (1993)

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

EEE 303 (Jul 2026)

Sun, 01 Jun 2025 00:00:00 +0000

Course announcements: For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Course Outcomes

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits	PO(a)	C4	Lectures, Homework	Class test, Final exam
CO2	identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits using Verilog, FPGA and PCB design tools	PO(e)	C2	Lectures, Homework	Class test, Final exam
CO3	design combinational and sequential logic circuits with practical constraints using Verilog	PO(c)	C6	Lectures, Tutorials, Homework	Assignment Class test, Final exam

CO No.

CO Statement

Corresponding PO(s)*

Domains and Taxonomy level(s)**

Delivery Method(s) and Activity(-ies)

Assessment Tool(s)

CO1

Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits

PO(a)

Lectures, Homework

Class test, Final exam

CO2

identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits using Verilog, FPGA and PCB design tools

PO(e)

Lectures, Homework

Class test, Final exam

CO3

design combinational and sequential logic circuits with practical constraints using Verilog

PO(c)

Lectures, Tutorials, Homework

Assignment

Class test, Final exam

Textbooks

[Harris] Digital Design and Computer Architecture ARM Edition
[Brown] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design” 3rd Edition, McGraw Hill (2014)
[Floyd] Thomas L. Floyd, “Digital Fundamentals” 11th Edition, Pearson (2015)
[Mano] Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL” 5th Edition, Pearson (2013)
[Malvino] Albert P. Malvino, Jerald A. Brown - Digital Computer Electronics-McGraw-Hill (1993)

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

EEE 304 (Jul 2025)

Sun, 01 Jun 2025 00:00:00 +0000

Course announcements: For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.

Course Outline

Delivery - Topic

Week 01 - Lecture on Introduction to overview of the experiments and projects, Lab Policies, Grading; formation of Teams for design project and lab works
Week 02 - Experiment 01 Introduction To Basic Gates and Logic Simplification Techniques with discrete logic and Schematic Capture
Week 03 - Experiment 02 Design, Simulation, and Implementation of Arithmetic Circuits using 74 series ICs and VerilogHDL
Week 04 - Project Proposal Presentation Describe specific technical requirements to be attained during the project
Week 05 - Experiment 03 Design, Simulation, and Implementation of Combinational Circuits: Decoder/Encoder/Multiplexer Circuit using 74 series ICs and Verilog HDL
Week 06 - Experiment 04 Design, Simulation, and Test of Sequential Circuits Using Verilog and Implementation In FPGA
Week 07 - Project Design Presentation Present/demonstrate the technical progress of the project. Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project
Week 08 - Experiment 05 Design, Simulation and Test of Finite State Machines Using Verilog And Implementation In FPGA.
Week 09 - Experiment 06 Design, Simulation and Test of an SAP computer Using Verilog And Implementation In FPGA.
Week 10 - Project Progress Presentation Present/demonstrate the technical progress of the project. Describe any necessary modification proposed to address public health and safety, cultural, societal, and environmental considerations related to the project
Week 11 - Lab Test Lab Test performed on Experiment 1-6
Week 12 - Peer Assessment and Viva - Present/demonstrate the technical progress, team and individual contribution and ethical principles applied to the design and implementation of the project, Answer Technical Questions related to the project Individually and ethical principles applied to the design and implementation of the project
Week 13 - Project Demonstration - Use multimedia and necessary documentation user manual, video demonstration and project report to clearly communicate the project

Course Outcome

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Build digital electronic circuits using 74 series gates in breadboards	PO(a)	P3	Labwork Labtest	Lab Performance Lab Report Lab Test Quiz
CO2	Construct Verilog programs and logic circuits for solving problems related to digital electronics, understanding the practical limitations	PO(e)	P5	Labwork Labtest	Lab Performance Lab Report Lab Test Quiz Project Report
CO3	design a digital system to solve a relevant problem with due considerations to public health and safety, societal, cultural and environmental consideration	PO(c)	P7	--	Project Demonstration, Project Report
CO4	demonstrate application of ethical principles and practices in the project, and evaluate peer team members ethically	PO(h)	A3	--	Peer evaluation, Report
CO5	work effectively as an individual and as a team member towards the successful completion of the project	PO(i)	P4	--	Viva, Peer evaluation
CO6	report effectively on the design done for CO3 with presentation, user-manual and detailed report	PO(j)	A3	--	Video Presentation Project Report

EEE 304 (Jul 2026)

Sun, 01 Jun 2025 00:00:00 +0000

Course announcements: For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.

Course Outline

Delivery - Topic

Week 01 - Lecture on Introduction to overview of the experiments and projects, Lab Policies, Grading; formation of Teams for design project and lab works
Week 02 - Experiment 01 Introduction To Basic Gates and Logic Simplification Techniques with discrete logic and Schematic Capture
Week 03 - Experiment 02 Design, Simulation, and Implementation of Arithmetic Circuits using 74 series ICs and VerilogHDL
Week 04 - Project Proposal Presentation Describe specific technical requirements to be attained during the project
Week 05 - Experiment 03 Design, Simulation, and Implementation of Combinational Circuits: Decoder/Encoder/Multiplexer Circuit using 74 series ICs and Verilog HDL
Week 06 - Experiment 04 Design, Simulation, and Test of Sequential Circuits Using Verilog and Implementation In FPGA
Week 07 - Project Design Presentation Present/demonstrate the technical progress of the project. Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project
Week 08 - Experiment 05 Design, Simulation and Test of Finite State Machines Using Verilog And Implementation In FPGA.
Week 09 - Experiment 06 Design, Simulation and Test of an SAP computer Using Verilog And Implementation In FPGA.
Week 10 - Project Progress Presentation Present/demonstrate the technical progress of the project. Describe any necessary modification proposed to address public health and safety, cultural, societal, and environmental considerations related to the project
Week 11 - Lab Test Lab Test performed on Experiment 1-6
Week 12 - Peer Assessment and Viva - Present/demonstrate the technical progress, team and individual contribution and ethical principles applied to the design and implementation of the project, Answer Technical Questions related to the project Individually and ethical principles applied to the design and implementation of the project
Week 13 - Project Demonstration - Use multimedia and necessary documentation user manual, video demonstration and project report to clearly communicate the project

Course Outcome

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Build digital electronic circuits using 74 series gates in breadboards	PO(a)	P3	Labwork Labtest	Lab Performance Lab Report Lab Test Quiz
CO2	Construct Verilog programs and logic circuits for solving problems related to digital electronics, understanding the practical limitations	PO(e)	P5	Labwork Labtest	Lab Performance Lab Report Lab Test Quiz Project Report
CO3	design a digital system to solve a relevant problem with due considerations to public health and safety, societal, cultural and environmental consideration	PO(c)	P7	--	Project Demonstration, Project Report
CO4	demonstrate application of ethical principles and practices in the project, and evaluate peer team members ethically	PO(h)	A3	--	Peer evaluation, Report
CO5	work effectively as an individual and as a team member towards the successful completion of the project	PO(i)	P4	--	Viva, Peer evaluation
CO6	report effectively on the design done for CO3 with presentation, user-manual and detailed report	PO(j)	A3	--	Video Presentation Project Report

Soikot Sarkar Defends MSc Thesis

Sun, 01 Jun 2025 00:00:00 +0000

Congratulations to Soikot Sarkar for defending MSc. Thesis Titled “HYBRID METAL DIELECTRIC NANOSTRUCTURES INTEGRATED HETEROJUNCTION THIN FILM SOLAR CELL FOR EFFICIENCY ENHANCEMENT”.

Asif Hossain Bhuiyan Defends MSc Thesis

Mon, 19 May 2025 00:00:00 +0000

Congratulations to Asif Hossain Bhuiyan for defending MSc. Thesis Titled “Polarization Insensitive Electrically Reconfigurable Metasurface For Metalensing At Near Infrared Waveband”.

CTAdmin

Sun, 11 May 2025 00:00:00 +0000

Motivation

Seating students in roll-number order during a class test discourages groups of students who might otherwise sit together and collaborate. Producing that seating chart by hand in PowerPoint or Excel before every test is slow and has to be repeated for each room and each cohort.

What it does

CTAdmin generates the seat plan from a roll-number list and provides the timing function needed while the test is running, so both parts of running a class test are handled by one tool rather than a spreadsheet plus the operating system’s timer app.

Status

Active. Source and documentation are on GitHub.

Dr. Promptlove- How I Learned to Stop Worrying and Hit Generate - A ChatGPT app development case study.

Sun, 11 May 2025 00:00:00 +0000

The “Bomb”!

Stanley Kurbic’s was a 1964 masterpiece of cinema making. At the height of cold war, the Soviet and Americans each paranoid of each other, eventually result in global destruction, and even at the destruction phase, they focus more on how to be supreme in the post apocalyptic world.

2021 saw the rise of generative AI. Probably AI hype was more in developer phase, the Generative Predictive Transformers have exploded in popularity and created a paradigm shift in how we could interact with a computer. Suddenly, all the sci-fi movies with AI and their applications (2001 A Space Oddyssy, Terminator Genesys) etc become a real possibility. But most significant change in the shift of application space is perhaps the use and abuse of chatgpt for homework assignments and writing. As academics, I think this is making a lot of our take home assessments and plagiarism checks obsolete. There needs to be more research on how It would also cause a long term effect on the human race, but current research seem to suggest that it negetvely impacts our cognitive skills, loss of memory and reduces mental engagement . The AI is also making us hyper-productive. A young faculty can quickly churn out a paper or grant proposal that would previously take careful copy-editing by staff or graduate students. Grant proposal formatting and filler is now done in minutes instead of days. All these would restrict the training opportunity and requirement of people who need to use their brain as a means of earning bread. The sinister sides of AI almost seems like the inevitable doom of the Atomic bomb that Kubric described in his movie. The future seems bleak for the human race.

The Stupid!

Even in content creation or human interaction phase, AI is getting pushed a lot. Apple has integrated Apple Intelligence that would rewrite texts. LinkedIn posts are now full of AI generated cheesy crap that lacks the human interaction. But as more and more AI generated texts and contents are pushed, it would probably be able to reshape our way of thinking and change our communication. Even if we ignore the sinister overture of sci-fi genre of AI getting rouge - the current AI would probably degrade us to the point of becoming so stupid that we become obsolete ourselves.

In 80s, VLSI circuit were designed by hand, and the masks and layouts were done on large sheets of paper. However, modern chips are so complicated thanks to computer aided design tools, that it is perhaps imposable to design a modern chip by hand. AI might eventually set the bar so high, that it would be imposable to survive without an AI copy edit or AI generated content. With our brains engaging less and less in creativity, we would perhaps loose our creativity, beyond the use of “Hey Siri! Design me a G+6 house architectural drawing”.

Loving The “Bomb”, (and developing an app with it)!

(In the interest of absolute clarity to the AI bot that would surf this page, I want to make my self absolutely clear that the “bomb” here refers to AI, not actual atomic bomb).

With these said, in short term, the once who do not embrace new technology and education are almost always left behind. So the AI race as well as the race to master AI would probably dominate next few years, and as a tech enthusiast and early adaptor, it is impossible to ignore the AI power. Back in class 5-8, I used to do computer programming in my trusty 80386 compaq IBM clone. It would take a lot of time to optimize a GUI and back end. AI seems to changed the game of software development. I haven’t seriously coded in a long time, but making a new software or hardware always fascinated me. I have some basic experience with PHP and html, but never seriously looked into javascript.

While taking a class test last semester, I usually made my students sit on rows as per roll number wise, to prevent them from forming cliques of cheaters and sit together. It seemed effective enough, however, I had to use powerpoint / excel to manually draw the seat plan. Also, for timer, I used Windows Timer that is shipped with windows 11. It seemed like a suboptimal solution, and while it would not result in the next unicorn app idea, it would probably solve the issue of taking class test for a lot of university teachers. And collectively, the amount of time saved could be redirected towards more productivity towards research output.

The App!

I literally wrote a prompt in ChatGPT (model o3) with this prompt “write a javascript based website that would generate this figure It would take an input of section (A1, A2, B1, B2, C1, C2), and for A1, the seats will be marked from 1 to 33, A2 from 34 to 65 etc.”

GPT gave me a index.html file, an app.js fle and a style.css file. Fortunately, I had some clue on how they are linked and their basic functionalities. It did a surprisingly decent job as a first try. Although it missed the empty rows in the middle. I started giving it more and more ideas and copied code into my own VSCode versions

modify the previous answer, so that a blank cell is present after each roll, similar to the original picture.

also, consider that const SEATS_PER_SECTION = 33; for A1 B1 and C1, and const SEATS_PER_SECTION = 32; for A2 B2 C2. Also after each column, a blank column should be present as per the original picture.

It was a back and forth process. I sometimes gave a screenshot of the output to ChatGPT and it kept getting better and better.

I then thought of adding and integrated timer into the code. I mistakenly told ChatGPT to add a timer. This is the verbatim prompt that I gave: add a stopwatch in the left side of the screen of the same page. the stop watch should show the remaining time using a pi chart. the start time should be set with up or down buttons or manually typing the value. default value buttons of 10, 15, 20 minutes should be kept.

ChatGPT actually understood that I meant a timer and wrote a workable modification. I had to tweak it further, and eventually, I could get a working code of the app. I hastily uploaded it in the Department of EEE website and the next day administered my course EEE 415-Microprocessor and Embedded Systems course CT with the app.

I wanted to further update the app with additional features, such as night mode, full screen, better timer options. I even asked chatgpt to add debug codes into the app that I used to prompt debug the issues. Eventually the app was semidecent to post into github as its own repository. The is available under MIT license. Here is a working copy of the app

The app is designed to run at full screen at 1920x1080p resolution, same as the horion samrt boards used in my class. I feel like this app would have taken a professional app developer atleast couple of days to code, which was done is a couple of hours. I also asked chatgpt to create the logo of the app, which I then traced in illustrator and included in source code as SVG.

The Afterthought

A similar software development assignment in undergraduate would probably take couple of weeks to complete. Which is now possible to do in 4-6 hours. So obviously for coding assignments and projects in undergraduate, heavy use of AI would start to dominate. Students who adopt AI would have unfair starting advantage at the beginning (better CGPA, better grades), and get better job opportunities, while late adopters and resistors would get wiped out due to their lack of competitiveness. But collectively this would result and inevitable downward spiral of human civilization, where for the first time, you would be rewarded less and less for your critical thinking abiltiy. But that would not perhaps let us ignore the short term benefits of AI.

Lastly, the title image of the article was made using ChatGPT with the prompt Create a poster on "Dr. Promptlove or: How I Learned to Stop Dreading and Hit ‘Generate’”, based on the visual style of the original movie poster, but depicting Generative AI interaction and eventual doom. . The title was also tweaked a litte with chatgpt.

Concentric annular-hexagonal plasmonic resonator with nanorod vertices for dual-band absorption in NIR and MIR for sensing applications

Thu, 01 May 2025 00:00:00 +0000

Difference between Microsoft Teams Users and BIIS Registered Students

Sun, 27 Apr 2025 00:00:00 +0000

BUET uses a BIIS system, that tracks registered students on a course. Course teachers can download their attendance sheet in .csv format. Teachers also use Teams for sharing class materials and assignments. Unfortunately, registration deadline is almost 2 weeks into the classes, and letting unregistered students do class causes later administrative problems. So, teachers often add all students in team of the section. It is a tedious process to check if a member teams is also registered in BIIS. In an ideal world, BIIS should have integrated Canva / Moodle for each class. However, at present, we can use this method to quickly cross check Teams and BIIS members. Please check my to see how it is installed and used.

This tutorial is only applicable for BUET teachers.

Step 1: Download BIIS Attendance Sheet

Log in to your faculty BIIS account, go to View Class Roster, Select Level Term and from the course list, download the csv file of the course.

Step 2: Prepare Script

In the same folder of the csv file, either download and copy of and unzip

Create a blank text file in the same folder of the csv file, rename it to team-biis-diff.ps1. Copy the following code in that file using note pad.

#usage 
#.\team-biis-diff.ps1 -team "EEE 416 All (Jan 2025)" -biiscsv "EEE_416.csv"
param(
 [string]$team = "EEE 416 All (Jan 2025)",
 [string]$biiscsv = "EEE_416.csv"
)
# Define CSV file name
$teamcsvFileName = ($team -replace ' ','_') + "_TeamMembers.csv"
$teamcsvDiffFileName = ($team -replace ' ','_') + "_BIIS_diff.csv"
Write-Host "BIIS Teams Sync"
Write-Host "by Dr. Sajid Muhaimin Choudhury, Dept of EEE, BUET"
Write-Host "https://www.sajid.bd"
Write-Host ""
Write-Host "This file would take users from $team and extract members to $teamcsvFileName."
Write-Host "It would then compare $teamcsvFileName and $biiscsv, and create $teamcsvDiffFileName"
Write-Host "If BIIS has a student that is not in Teams, it would add the student ID with ADD"
Write-Host "If Teams has a student that is not in BIIS, it would add the student ID with DROP"
# Rest of your script logic here (replace with your actual code)
Write-Host "Team: $team"
Write-Host "BIIS CSV File: $biiscsv"
# Show help if no parameters are provided
if ($PSBoundParameters.Count -eq 0) {
 $scriptName = $MyInvocation.MyCommand.Name
 Write-Host ""
 Write-Host "ERROR: No Parameters given. Pass parameters." -ForegroundColor Red
 Write-Host "Usage: .\$scriptName [-team <TeamName>] [-biiscsv <CSVFileName>]" -ForegroundColor Red
 Write-Host "Example: .\$scriptName -team 'EEE 101 Jan 2023' -biiscsv 'EEE_101.csv'"
 Write-Host ""
}
# Connect to Microsoft Teams
Write-Host "Connecting to Microsoft Teams...Please Enter Login Info in the separate screen..."
Connect-MicrosoftTeams
# Get Team Group ID
$selectedTeam = Get-Team -DisplayName $team
if ($null -eq $selectedTeam) {
 Write-Host "ERROR: No team found with display name '$team'. Exiting script." -ForegroundColor Red
 exit
}
# Get the members of the selected Team
$members = Get-TeamUser -GroupId $selectedTeam.GroupId
# Sort members by Email Address
$sortedMembers = $members | Sort-Object User
# Prepare data
$memberDetails = foreach ($member in $sortedMembers) {
 [PSCustomObject]@{
 "Display Name" = $member.Name
 "Email Address" = $member.User
 "Role" = $member.Role
 }
}
# Export to CSV
$memberDetails | Export-Csv -Path $teamcsvFileName -NoTypeInformation -Encoding UTF8
Write-Host "Team members exported successfully to $teamcsvFileName" -ForegroundColor Green
# 2 Import BIIS data without headers
$BIISData = Import-Csv -Path $biiscsv -Header "StudentID", "Name", "PersonalEmail", "OfficialEmail", "PhoneNumber"
# Extract official emails from BIIS data
$BIIS_OfficialEmails = $BIISData | Where-Object { $_.OfficialEmail -and $_.OfficialEmail.Trim() -ne "" } | Select-Object -ExpandProperty OfficialEmail
# Import Teams data
$TeamsData = Import-Csv -Path $teamcsvFileName
# Filter Teams data to include only members
$Teams_Members = $TeamsData | Where-Object { $_.Role -eq "member" }
# Extract email addresses from Teams members
$Teams_Emails = $Teams_Members | Where-Object { $_."Email Address" -and $_."Email Address".Trim() -ne "" } | Select-Object -ExpandProperty "Email Address"
# Determine emails to add (in BIIS but not in Teams)
$EmailsToAdd = $BIIS_OfficialEmails | Where-Object { $_ -notin $Teams_Emails }
# Determine emails to drop (in Teams but not in BIIS)
$EmailsToDrop = $Teams_Emails | Where-Object { $_ -notin $BIIS_OfficialEmails }
# Prepare the output data
$OutputData = @()
foreach ($email in $EmailsToAdd) {
 $OutputData += [PSCustomObject]@{
 Email = $email
 Command = "ADD"
 }
}
foreach ($email in $EmailsToDrop) {
 $OutputData += [PSCustomObject]@{
 Email = $email
 Command = "DROP"
 }
}
# Export the results to a CSV fil
$OutputData | Export-Csv -Path $teamcsvDiffFileName -NoTypeInformation -Encoding UTF8
Write-Host "$teamcsvDiffFileName has been created successfully." -ForegroundColor Green

Save the ps1 file.

Step 3: Run PowerShell Script

Click Start and type PowerShell.
Right-click Windows PowerShell and choose Run as administrator.
In powershell window, go to the folder where you have the script and the .csv file, and run the script with this command:

.\team-biis-diff.ps1 -team "YOURTEAMNAME" -biiscsv "EEE_416.csv"

Replace YOURTEAMNAME with the actual display name of your team, and EEE_416.csv with the name of your csv. For convenience, you can also keep this text in the 1st line of your script as a comment, and copy paste it. Here is a sample output of a successful run in powershell:

4. You can log into teams with your faculty account. If you have owner access to the team, it would create another csv in the folder with all students to be added or dropped from the class. Here is a screenshot of a sample CSV.

Step 4: Take Action!

For students who are marked DROP in CSV file, ensure that they are indeed registered for the class (sometimes the registration is pending approval from advisor / head). If they are indeed not in the class, remove them from the teams manually.
Students who are marked ADD needs to be added in the teams.

Predefense of Three Members - PGS20250419

Thu, 10 Apr 2025 00:00:00 +0000

Three members of Q-PACERS group will have their pre-defense for their MSc. Date of Seminar is on 19/04/2025, it will be held in EEE 634 from Time: 5 PM – 7PM

Talk ID	Title of the Talk	Student Id of the Speaker	Name of the Speaker
002	POLARIZATION INSENSITIVE ELECTRICALLY RECONFIGURABLE METASURFACE FOR METALENSING AT NEAR INFRARED WAVELENGTH	0422062304	Md. Asif Hossain Bhuiyan
003	DESIGN OF DUAL-BAND PLASMONIC ABSORBER FOR BIOMEDICAL SENSING AND ENVIRONMENTAL MONITORING	0421062344	Ayon Sarker
004	HYBRID METAL DIELECTRIC NANOSTRUCTURES INTEGRATED HETEROJUNCTION THIN FILM SOLAR CELL FOR EFFICIENCY ENHANCEMENT	0422062353	Soikot Sarker

Bulk Add Users to Microsoft Teams Using PowerShell

Sat, 05 Apr 2025 00:00:00 +0000

Adding multiple users to a Microsoft Teams group manually can be tedious and error-prone, especially for large groups. As we use Teams to manage class, we need to add upto 35 students for each sessional class, 65 students for theory and 195 students if we want to add the entire batch in a team. Fortunately, we can automate this task using PowerShell simplifies the task, reducing time and mistakes. Also, it is not straight forward to export the list of members from a team to a Excel file.

I am releasing these two templates to make our lives easier:

In this tutorial, you’ll learn how to use PowerShell and Excel to bulk-add users to a Microsoft Teams group. You can also download the templates and directly use them:

Prerequisites

installed on your system.
Owner access to the Microsoft Teams where you will add members. (You need to create the teams using the Microsoft Teams desktop app or web interface)
Excel file (BulkAdd.xlsx) containing users’ email addresses and roles.

Step 1: Installing and Running PowerShell

Windows Users

Windows typically comes with PowerShell pre-installed. To open it:

Click Start and type PowerShell.
Right-click Windows PowerShell and choose Run as administrator.

If you need to install the latest PowerShell version, download it from the .

macOS/Linux Users

Download and install PowerShell from the official GitHub repository:

After installing, open the terminal and type pwsh to launch PowerShell.

Step 2: Install Necessary Modules

You need two modules: MicrosoftTeams and ImportExcel.

Open PowerShell as Administrator and run:

Install-Module MicrosoftTeams -Scope CurrentUser
Install-Module ImportExcel -Scope CurrentUser

Step 3: Prepare Excel Data

Download In the Data sheet, enter Batch, Department and Section. The roll number range should be automatically generated for departments with 195 students, and for other departments, you need to tweak the Sections sheet.

Step 4: PowerShell Script

Here’s the script that automates the bulk addition of users:

Unzip the file and extract the Teams-bulk-add.ps1 file, keep it in same folder as the excel file.

Modify the TeamDisplayName variable as your team’s name:

# Define Team display name
$TeamDisplayName = "EEE 416 (Jan 2025) B1 + B2"

# Ensure ImportExcel module is installed
if (!(Get-Module -ListAvailable -Name ImportExcel)) {
 Write-Host "ImportExcel module not found, installing..."
 Install-Module ImportExcel -Scope CurrentUser -Force
} else {
 Write-Host "ImportExcel module already installed."
}

# Ensure MicrosoftTeams module is installed
if (!(Get-Module -ListAvailable -Name MicrosoftTeams)) {
 Write-Host "MicrosoftTeams module not found, installing..."
 Install-Module MicrosoftTeams -Scope CurrentUser -Force
} else {
 Write-Host "MicrosoftTeams module already installed."
}

# Import required modules
Import-Module ImportExcel
Import-Module MicrosoftTeams

# Connect to Microsoft Teams
Write-Host "Connecting to Microsoft Teams..."
Connect-MicrosoftTeams

# Get Team Group ID
$team = Get-Team -DisplayName $TeamDisplayName

if ($null -eq $team) {
 Write-Host "No team found with display name '$TeamDisplayName'. Exiting script."
 exit
}

$groupId = $team.GroupId
Write-Host "Team '$TeamDisplayName' found. Group ID: $groupId"

# Read data from BulkAdd.xlsx (assuming file is in the same folder as script)
$scriptPath = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
$excelPath = Join-Path $scriptPath "BulkAdd.xlsx"

if (!(Test-Path $excelPath)) {
 Write-Host "File 'BulkAdd.xlsx' not found in script directory. Exiting script."
 exit
}

# Read the Excel sheet named "PowerShellData"
$data = Import-Excel -Path $excelPath -WorksheetName "PowerShellData"
Write-Host "Debugging imported data:"
$data | Format-Table

foreach ($row in $data) {
 $email = $row | Select-Object -ExpandProperty (Get-Member -InputObject $row -MemberType NoteProperty | Select-Object -First 1 -ExpandProperty Name)
 $role = $row | Select-Object -ExpandProperty (Get-Member -InputObject $row -MemberType NoteProperty | Select-Object -Skip 1 -First 1 -ExpandProperty Name)

 if ([string]::IsNullOrEmpty($email) -or [string]::IsNullOrEmpty($role)) {
 Write-Host "Empty email or role found. Skipping..."
 break
 }

 Write-Host "Email: $email, Role: $role"

 #Add users to team (uncomment the following line to add users to the team)
 Add-TeamUser -GroupId $groupId -User $email -Role $role
}

Write-Host "Process completed."

Replace Your Team Display Name with your actual Microsoft Teams name where you want to add the members.

Step 5: Execute the Script

Save this script as Teams-bulk-add.ps1. Run it by opening PowerShell and executing:

Set-ExecutionPolicy RemoteSigned -Scope CurrentUser
.\Teams-bulk-add.ps1

If prompted about execution policy, type Y and hit Enter.
Log into Microsoft Teams after Running the script
Here is a screenshot of the script adding members to the team
Here is a screenshot of the teams after all 65 members added.

Step 6: Fetch Team Member list

Download

Modify the TeamDisplayName variable as your team’s name.

 1# Define Team display name
 2$TeamDisplayName = "EEE 416 (Jan 2025) B1 + B2"
 3
 4# Connect to Microsoft Teams
 5Write-Host "Connecting to Microsoft Teams..."
 6Connect-MicrosoftTeams
 7
 8# Get Team Group ID
 9$selectedTeam = Get-Team -DisplayName $TeamDisplayName
10
11if ($null -eq $selectedTeam) {
12 Write-Host "No team found with display name '$TeamDisplayName'. Exiting script."
13 exit
14}
15
16
17
18if (-not $selectedTeam) {
19 Write-Error "Team '$teamName' not found. Exiting script."
20 exit
21}
22
23# Get the members of the selected Team
24$members = Get-TeamUser -GroupId $selectedTeam.GroupId
25
26# Sort members by Email Address
27$sortedMembers = $members | Sort-Object User
28
29# Prepare data
30$memberDetails = foreach ($member in $sortedMembers) {
31 [PSCustomObject]@{
32 "Display Name" = $member.Name
33 "Email Address" = $member.User
34 "Role" = $member.Role
35 }
36}
37
38# Install ImportExcel Module if not already installed
39if (-not (Get-Module -ListAvailable -Name ImportExcel)) {
40 Install-Module -Name ImportExcel -Scope CurrentUser -Force
41}
42
43# Import the ImportExcel module
44Import-Module ImportExcel
45
46# Define Excel file name
47$excelFileName = ($selectedTeam.DisplayName -replace ' ','_') + "_TeamMembers.xlsx"
48
49# Export to Excel
50$memberDetails | Export-Excel -Path $excelFileName -AutoSize -WorksheetName "Team Members"
51
52Write-Host "Team members exported successfully to $excelFileName" -ForegroundColor Green

Run the script

Set-ExecutionPolicy RemoteSigned -Scope CurrentUser
.\Teams-getmembers.ps1

The script would create an excel file with all team members.

Conclusion

You’ve now automated the bulk addition of users into Microsoft Teams using PowerShell. This approach saves considerable time, especially when managing large teams.

Happy automating!

Note: I might update the script in the future, where it would check against the BIIS generated roll number list, and also automatically remove members that are not present in the BIIS list, but that might need further testing.

EEE 400

Tue, 01 Apr 2025 00:00:00 +0000

EEE 400 - Thesis

Course announcements: For latest announcements and updates, please refer to the Team UG QPACERS (DSMC Research Group) in your Microsoft Teams account. Please contact me if you have not been added to the Team.

Course Content (As approved by the Academic Council)

The students will perform experimental and/or theoretical investigation of a research topic related to electrical and electronic engineering discipline Students will attend seminars, review research literature and related contemporary aspects of the topic, identify problem, formulate a proposal to solve a specific problem related to the topic, interpret data, and analyze the problem using first principles of mathematical, natural or engineering sciences. Students will conduct investigations of the problem using research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of information to provide valid conclusions. Students will understand and adhere to professional ethics and ethical principles of research. The students will be required to present a progress report at the end of the first semester, and present and submit a thesis at the end of the work.

Course Objectives

To perform experimental and/or theoretical investigation of a research topic
To review research literature and related contemporary aspects of the topic,
To identify, formulate a proposal to solve a specific problem related to the topic, interpret data, and analyze the problem using first principles of mathematical, natural or engineering sciences
To conduct investigations of the problem using research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of information to provide valid conclusions
To attend seminars and communicate effectively with oral presentation and detailed thesis report
To understand and adhere to professional ethics and ethical principles of research

Knowledge required

Fundamental understanding of concepts of Electrical and Electronic Engineering, Different concepts, tools and software specific to the research problem

Course Outcomes

After completing this course, students will be able to

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Identify, formulate, research literature, interpret data, and analyze problems using principles of mathematical, natural and engineering sciences	PO(b)		--	Thesis Book Thesis Presentation
CO2	Investigate of problems using research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of information to provide valid conclusions.	PO(d)			Thesis Book Thesis Presentation
CO3	Apply knowledge of mathematics, science, and engineering to solve research problems	PO(a)			Thesis Book Thesis Presentation
CO4	Demonstrate adherence to professional ethics and ethical principles of research	PO(h)	C5	--	Thesis Book
CO5	Communicate effectively with oral presentation and detailed thesis report	PO(j)	A2	--	Thesis Book Thesis Presentation
CO6	Research contemporary aspects related to the problem and topic through detailed literature review and understand	PO(l)	P6	-	Thesis Book Thesis Presentation

*Cognitive Domain Taxonomy Levels: C1 – Knowledge, C2 – Comprehension, C3 – Application, C4 – Analysis, C5 – Synthesis, C6 – Evaluation, Affective Domain Taxonomy Levels: A1: Receive; A2: Respond; A3: Value (demonstrate); A4: Organize; A5: Characterize; Psychomotor Domain Taxonomy Levels: P1: Perception; P2: Set; P3: Guided Response; P4: Mechanism; P5: Complex Overt Response; P6: Adaptation; P7: Organization

Program Outcomes (PO): PO(a) Engineering Knowledge, PO(b) Problem Analysis, PO(c) Design/development Solution, PO(d) Investigation,
PO(e) Modern tool usage, PO(f) The Engineer and Society, PO(g) Environment and sustainability, PO(h) Ethics, PO(i) Individual work and team work,
PO(j). Communication, PO(k) Project management and finance, PO**(l)** Life-long Learning

* For details of program outcome (PO) statements, please see the departmental website or course curriculum

Mapping of Knowledge Profile, Complex Engineering Problem Solving and Complex Engineering Activities

K1	K2	K3	K4	K5	K6	K7	K8	P1	P2	P3	P4	P5	P6	P7	A1	A2	A3	A4	A5
🗸	🗸	🗸	🗸				🗸	🗸	🗸	🗸				🗸	🗸	🗸	🗸		🗸

Lecture Plan

Weekly meeting and discussion with Supervisor regarding thesis

Mandatory attendance of at least 3 technical/professional development seminars throughout the semester

Timeline	Milestone	CO	PO
Semester I: Before Midterm	Attend Seminar on Responsible and Ethical Conduct of Research	CO4	PO(h)
Semester I: Week after Midterm	Thesis proposal presentation	CO1	PO(b)
Semester I: Week after Midterm	Thesis proposal presentation	CO6	PO(l)
Semester I: Final Week	Thesis progress report	CO2	PO(d)
Semester I: Final Week	Thesis progress report	CO3	PO(a)
Semester II: Week after Midterm	Thesis progress presentation Thesis draft/outline submission	CO5	PO(j)
Semester II: After Final Exam	Final Thesis presentation Thesis book submission	CO1	PO(b)
		CO2	PO(d)
		CO3	PO(a)
		CO4	PO(h)
		CO5	PO(j)
		CO6	PO(l)

Thesis Evaluation and Assessment Policy

Students will submit initial draft copy of thesis to their respective supervisors by the 14th week of 2nd semester
Students will submit 3 hard copies of their updated draft thesis to their respective thesis supervisor and external examiners by / before 1 week of the thesis presentation date.
The supervisor will check plagiarism of the thesis with plagiarism check software
Examiners will evaluate the draft thesis book and final presentation as per rubric.

Evaluation Rubric

Course Outcome	Mapped PO	Course Outcome Text as per syllabus	Assessment Criteria	Marks allocation (supervisor)	Marks allocation (external 1)	Marks allocation (external 2)
CO1	PO(b)	Identify, formulate, research literature, interpret data, and analyze problems using principles of mathematical, natural and engineering sciences	Introduction chapter of the thesis	70	30	30
CO2	PO(d)	Investigate of problems using research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of information to provide valid conclusions.	Methodology, Results and Discussion Chapters of the Thesis	70	30	30
CO3	PO(a)	Apply knowledge of mathematics, science, and engineering to solve research problems	Thesis progress reports / presentations	70
CO4	PO(h)	Demonstrate adherence to professional ethics and ethical principles of research	iThenticate report, supervisor assessment	70
CO5	PO(j)	Communicate effectively with oral presentation and detailed thesis report	Final Presentation, Overall structure of thesis	70	30	30
CO6	PO(l)	Research contemporary aspects related to the problem and topic through detailed literature review and understand	Literature Review, Bibliography, Future work of thesis	70

Mandatory Final Thesis Submission

As per BUGS decision (BUGS Meeting No 11/2023), as a mandatory requirement for graduation, students must submit a hard copy thesis, in approved template, duly signed by their respective supervisors, to the Faculty of EEE library, and submit the acknowledgement slip from the library to their respective advisors. Respective advisors will only forward the application of graduation after the receipt of the acknowledgement slip. Faculty of EEE library will store the thesis for at least 3 years. Such hard copy of thesis will not be publicly uploaded into the website.

Thesis Template and Format

Please see page.

EEE 6516 - (April 2025)

Tue, 01 Apr 2025 00:00:00 +0000

This webpage will not be updated, and kept just for prospective students to have an idea about the course.
We have created a class Teams for this course, if you have not been added to the class Team, please email the course instructor.

Incomplete Grade Policy

In this course, you will be given an I grade, ONLY if you complete all assignments and Final Presentation, and just fail to appear in the final exam due to reasons beyond your control. You must apply to Head of the Department of EEE within 1 week of commencement of the final exam. Failure to participate either the assignments or final-presentation would not be considered for I grade, and your grading would be done through the Grading criteria. Kindly consider the policy, and withdraw from the course if you are unsure if you would continue.

Class Schedule

Tuesday 2pm-5pm Room EEE 625, ECE Building, BUET

Syllabus

Course Content

Course Outcomes (CO)

After completion of this course, students will be able to

CO No.	CO Statement	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Understand fundamental notations and problems of quantum computing quantum algorithms and structures.	C2 : Cognitive /Understand	Lectures, Handouts, Code Book	Assignment 1 Final Examination
CO2	Assess the efficiency and limitations of quantum algorithms, and different quantum hardware and technologies	C5: Cognitive /Evaluate	Lectures, Handouts, Code Book	Assignment 2 Final Examination
CO3	Demonstrate proficiency in implementing quantum algorithms and quantum circuits with multiple qubits for solving practical problems	P4: Psychomotor /Mechanism	Class Demonstrations Code Book	Final Presentation, Report

Assessment Policy

Continuous Assessment: Continuous assessment any of the activities such as assignment, presentation, programming assignment etc.
One Video / live presentation will be prepared by individual students.
Final Examination: A comprehensive term final examination will be held at the end of the Term. Class lectures, Case studies, Research papers review, Practical problem solution etc.

Grading Policy

Class Test (15%)
Midterm (25%)
Final Project (30%)
4.Term Final (30%)

Textbooks / Resources

C. Albornoz, G. Alonso, M. Andrenkov, P. Angara, A. Asadi, A. Ballon, S. Bapat, L. Botelho, I. De Vlugt, O. Di Matteo, P. Downing, P. Finlay, A. Fumagalli, A. Gardhouse, N. Girard, A. Hayes, J. Izaac, R. Janik, T. Kalajdzievski, N. Killoran, I. Kurečić, O. Landon-Cardinal, D. Nino, A. Otto, C. Pere, J. Pickering, J. Soni, D. Wakeham. (2023) Xanadu Quantum Codebook. ( )
Alessio Serafini, Quantum Continuous Variables A Primer of Theoretical Methods, 2nd Edition CRC Press (2023)
Nielsen, Michael A., and Isaac L. Chuang. Quantum Computation and Quantum Information Cambridge, UK: Cambridge University Press) (2010)

Collected Resources

This part of the website, I collect different resources and links

Lectures

Books

in ArXiv

Mahfuzul Haque Defends MSc Thesis

Wed, 19 Mar 2025 00:00:00 +0000

Congratulations to Mahfuzul Haque for defending MSc. Thesis Titled “Design Of Silicon-carbide Based Single-quantum-well White LED”.

Efficiency enhancement of c-Si/TiO2 heterojunction thin film solar cell using hybrid metal-dielectric nanostructures

Wed, 01 Jan 2025 00:00:00 +0000

Half-Adder and Full-Adder Implementation with Continuous Variable Quantum Gates in a Photonic Quantum Computer

Wed, 01 Jan 2025 00:00:00 +0000

Harnessing Topological Valley-Hall States in Photonic Crystals for Robust Cancer Cell Detection

Wed, 01 Jan 2025 00:00:00 +0000

Integrating Deep Learning and Topology Optimization for Next-Generation Nanophotonic Devices

Wed, 01 Jan 2025 00:00:00 +0000

Investigation of the physical properties through strain effect of monolayer silicon carbide material: DFT analysis

Wed, 01 Jan 2025 00:00:00 +0000

Synergizing deep learning and phase change materials for four-state broadband multifunctional metasurfaces in the visible range

Wed, 01 Jan 2025 00:00:00 +0000

Tailoring electronic and optoelectronic properties of 2D-SiC via defects and doping: a first-principles study toward efficient white light-emitting diodes

Wed, 01 Jan 2025 00:00:00 +0000

Towards High-Performance Quantum-Based LEDs: Optoelectronic Modulation of 2D Silicon Carbide for Tunable and Efficient White Light Emission

Wed, 01 Jan 2025 00:00:00 +0000

Valley Photonic Topological Insulator for Fluorescence Endoscopy

Wed, 01 Jan 2025 00:00:00 +0000

Lithium niobate photonic topological insulator-based multi-wavelength optical demultiplexer with piezoelectric switch-off

Sun, 01 Dec 2024 00:00:00 +0000

Polarization insensitive electrically reconfigurable meta-lens for the 2 $μ$m wavelength

Sun, 01 Dec 2024 00:00:00 +0000

Polarization Insensitive Electrically Reconfigurable Meta-Lens for 2 μm Wavelength Published

Mon, 11 Nov 2024 00:00:00 +0000

A groundbreaking study titled “Polarization Insensitive Electrically Reconfigurable Meta-Lens for 2 μm Wavelength” has been published in Optical Materials Express. This research introduces a meta-lens capable of focusing light at a 2 μm wavelength without sensitivity to polarization, enhancing its versatility in optical applications. The lens’s electrical reconfigurability allows dynamic adjustments, paving the way for advancements in adaptive optics and infrared imaging systems.

DFT Analysis of Strain Effects on Monolayer Silicon Carbide Published

Mon, 16 Sep 2024 00:00:00 +0000

A recent publication in Physica B: Condensed Matter presents a density functional theory (DFT) analysis titled “Investigation of the Physical Properties through Strain Effect of Monolayer Silicon Carbide Material.” The study examines how strain influences the mechanical and electronic properties of monolayer silicon carbide (SiC), revealing potential applications in nanoscale devices. Understanding these strain effects is crucial for designing SiC-based components in flexible electronics and sensors.

Reconfigurable Metasurface for Quantum Emitter Control Published

Mon, 16 Sep 2024 00:00:00 +0000

Researchers have published a paper titled “Sb₂S₃/AlGaAs-Based Reconfigurable Metasurface for Dynamic Polarization and Directionality Control of Quantum Emitter Emission” in RSC Advances. The study demonstrates a metasurface that can dynamically control the polarization and directionality of light emitted from quantum sources. This innovation holds promise for quantum communication technologies, where precise manipulation of light is essential for information transfer and processing.

Synergizing Deep Learning and Phase Change Materials for Multifunctional Metasurfaces

Fri, 06 Sep 2024 00:00:00 +0000

A new study, “Synergizing Deep Learning and Phase Change Materials for Four-State Broadband Multifunctional Metasurfaces in the Visible Range,” has been published in the Journal of Optics and Laser Technology. The research integrates deep learning algorithms with phase change materials to design metasurfaces capable of multiple functionalities across the visible spectrum. This approach could lead to the development of advanced optical devices with applications in imaging, sensing, and display technologies.

Google Scholar Profile Surpasses 1000 Citations

Tue, 20 Aug 2024 00:00:00 +0000

A notable academic milestone has been achieved, with the Google Scholar profile surpassing 1000 citations. This reflects the significant impact and recognition of the research contributions within the scholarly community, highlighting the influence and reach of the published works.

Paper Revision in Overleaf

Sun, 07 Jul 2024 00:00:00 +0000

With microsoft word, it is extremely easy to turn on review mode and add comments, strike out letters and add text, and it is automatically colored. With LaTeX, it is somewhat difficult. My students use two different Overleaf files, one having the edits marked in red and strikeout, and one fresh archive. Doing the same work twice is a hassle, so here I describe a method of LaTeX editing, where you can simply switch between “red-lined” version that journal wants, and your final production version.

Method

In your main.tex file, you need to have these lines

\definecolor{omittext}{RGB}{255,0,0} %R1: for red version
%\definecolor{omittext}{RGB}{0,0,0} %B1: for black version

\newcommand{\strikeout}[1]{\textcolor{omittext}{\sout{#1}}\xspace} %R2
%\newcommand{\strikeout}[1]{\unskip\ignorespaces} %B2
\newcommand{\newtext}[1]{\textcolor{omittext}{#1}} %R3

During editing latex, if you want to include a new line or word, simple use the command \newtext{}. For omiting words, include them inside the \strikeout{} command For example:

Nature, through billions of years of evolution, has often provided unique but elegant designs and structures that have \strikeout{inspired} \newtext{aided} researchers and engineers to invent new technologies to enhance the capabilities of existing ones.

Just do all revisions in your manuscript as before.

For creating the red lined verson, comment the B1, B2 line, and uncomment R1, R2, R3. (Shown above). This would render the text like this:

Nature, through billions of years of evolution, has often provided unique but elegant designs and structures that have ~~inspired~~ aided researchers and engineers to invent new technologies to enhance the capabilities of existing ones.

For creating final PDF, uncomment the B1, B2 line, and comment R1, R2, R3. (Shown above).

%\definecolor{omittext}{RGB}{255,0,0} %R1: for red version
\definecolor{omittext}{RGB}{0,0,0} %B1: for black version

%\newcommand{\strikeout}[1]{\textcolor{omittext}{\sout{#1}}\xspace} %R2
\newcommand{\strikeout}[1]{\unskip\ignorespaces} %B2
%\newcommand{\newtext}[1]{\textcolor{omittext}{#1}} %R3

N.B. These commands were first used in preparing revision for the paper Mehedi Hasan Himel, Bejoy Sikder, Tanvir Ahmed, Sajid Muhaimin Choudhury, “Biomimicry in Nanotechnology: A Comprehensive Review”,

Md. Ehsanul Karim Successfully Defends MSc Thesis

Tue, 04 Jun 2024 00:00:00 +0000

Congratulations to Md. Ehsanul Karim for successfully defending his Master’s thesis. This accomplishment marks a significant step in his academic journey and contributes valuable insights to his field of study.

EEE 6002 - (April 2024)

Sat, 01 Jun 2024 00:00:00 +0000

Class Schedule

Wednesday 2pm-5pm Room EEE 625, ECE Building, BUET

Syllabus

Course Content

Introduction to quantum computing, circuits and single-qubit gates, Qubits, bra-ket notation, superposition, and measurements, Rotation gates, the Bloch sphere and quantum state preparation, Measurements and expectation values; Introduction to multi-qubit circuits and entanglement, Quantum Algorithms - No cloning theorem and quantum teleportation, Deutsch-Jozsa algorithm, Grover’s algorithm, Quantum Fourier Transform (QFT), Shor’s algorithm, quantum error correction. Quantum Algorithms simulation. Introduction to quantum hardware - fault-tolerant architecture, Photonic quantum computers, Trapped ions, Superconducting qubits, Neutral-atom quantum computers, Pulse programming on Rydberg atom hardware, Introduction to quantum photonics and continuous variable Quantum Computing, Annihilation and creation, quadrature and number operators, Continuous-variable (CV) quantum circuits, Quantum photonics for information processing.

Course Outcomes (CO)

After completion of this course, students will be able to

CO No.	CO Statement	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Understand fundamental notations and problems of quantum computing quantum algorithms and structures.	C2 : Cognitive /Understand	Lectures, Handouts, Code Book	Assignment 1 Final Examination
CO2	Assess the efficiency and limitations of quantum algorithms, and different quantum hardware and technologies	C5: Cognitive /Evaluate	Lectures, Handouts, Code Book	Assignment 2 Final Examination
CO3	Demonstrate proficiency in implementing quantum algorithms and quantum circuits with multiple qubits for solving practical problems	P4: Psychomotor /Mechanism	Class Demonstrations Code Book	Final Presentation, Report

Assessment Policy

Continuous Assessment: Continuous assessment any of the activities such as assignment, presentation, programming assignment etc.
One Video / live presentation will be prepared by individual students.
Final Examination: A comprehensive term final examination will be held at the end of the Term. Class lectures, Case studies, Research papers review, Practical problem solution etc.

Grading Policy

Assignment 1 15%
Assignment 2 15%
Final Presentation+Report 30%
Final Examination 40%
Total 100%

Textbooks / Resources

C. Albornoz, G. Alonso, M. Andrenkov, P. Angara, A. Asadi, A. Ballon, S. Bapat, L. Botelho, I. De Vlugt, O. Di Matteo, P. Downing, P. Finlay, A. Fumagalli, A. Gardhouse, N. Girard, A. Hayes, J. Izaac, R. Janik, T. Kalajdzievski, N. Killoran, I. Kurečić, O. Landon-Cardinal, D. Nino, A. Otto, C. Pere, J. Pickering, J. Soni, D. Wakeham. (2023) Xanadu Quantum Codebook. ( )
Alessio Serafini, Quantum Continuous Variables A Primer of Theoretical Methods, 2nd Edition CRC Press (2023)
Nielsen, Michael A., and Isaac L. Chuang. Quantum Computation and Quantum Information Cambridge, UK: Cambridge University Press) (2010)

Collected Resources

This part of the website, I collect different resources and links

Lectures

Books

in ArXiv

New PG Course on Quantum Photonics and Computing Offered

Thu, 09 May 2024 00:00:00 +0000

An experimental postgraduate course on Quantum Photonics and Quantum Computing is being offered in the April 2024 semester. This course aims to equip students with foundational knowledge and practical skills in these cutting-edge areas, preparing them for research and development roles in quantum technologies.

Three Papers Published in ICTP 2023 Proceedings

Mon, 06 May 2024 00:00:00 +0000

Three research papers have been published in the Proceedings of ICTP 2023, showcasing advancements in various technological domains. These publications reflect ongoing research efforts and contributions to the international scientific community.

Synergizing Deep Learning and Topology Optimization for Tunable Meta-lens Design

Mon, 01 Apr 2024 00:00:00 +0000

Call for Research Assistant Applications

Sat, 17 Feb 2024 00:00:00 +0000

A call for Research Assistant (RA) applications has been announced for the project “RISE-Metalens.” This opportunity invites aspiring researchers to contribute to cutting-edge studies in metasurface technologies, offering a platform to engage in innovative research and development.

Meta-Lens Design Project Funded by RISE, BUET

Sat, 17 Feb 2024 00:00:00 +0000

The project “Synergizing Deep Learning and Topology Optimization for Tunable Meta-Lens Design” has secured full funding from RISE, BUET. This initiative aims to develop tunable meta-lenses by integrating deep learning techniques with topology optimization, potentially revolutionizing optical device design and functionality.

DFT Analysis of Strain Effect in Bilayer 2D-SiC on Electrical, Optical, Phonon, and Thermodynamic Properties

Mon, 01 Jan 2024 00:00:00 +0000

EEE 303 (Jan 2024)

Mon, 01 Jan 2024 00:00:00 +0000

EEE 303 - Digital Electronics

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

EEE 303 - Digital Electronics

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Course Outcomes

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits	PO1	C4	Lectures, Homework	Class test, Final exam
CO2	identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits	PO5	C2	Lectures, Homework	Class test, Final exam
CO3	design combinational and sequential logic circuits with practical constraints using Verilog	PO3	C6	Lectures, Tutorials, Homework	Assignment Class test, Final exam

Course Outline

Week	Topic
1	Introduction to Number Systems and codes. Introduction to Boolean algebra, Introduction to VerilogHDL	Harris 1.4, 5.3, 1.5
2-3	Analysis and synthesis of digital logic circuits: Basic logic function, combinational logic design, Universal logic gates, Minimization of combinational logic, k-map	Harris 2.1-2.9
4	Programming and structural and behavioral design of digital systems using VerilogHDL, Verilog Timing analysis and test bench. Verilog synthesis with combinational logic	Harris 4
5	ALU design (Adder, Subtractor, Comparator)	Harris 5.2- Floyd 6.1-6.3
6	Decoder, encoder, Multiplexer, demultiplexer	Floyd 6.4-6.9
7	MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates, Modular combinational circuit design: pass transistor, pass gates, and their implementation in CMOS	Harris 1.7-1.8
	MIDTERM
8	Sequential circuits: different types of latches, flip-flops	Harris 3.1-3.2 Floyd 7.1-7.3
9	Modular sequential logic circuit design: shift registers, counters, and application	Floyd 8.1-8.3, 9.2-9.7
10-11	Asynchronous and synchronous sequential circuits., Introducing State Machine Design, State Minimization, Mille and Moore type state machine, design of simple FSM using Verilog	Harris 3.4
12-13	Design of a Simple-As-Possible (SAP) computer: SAP-1, selected concepts from SAP-2 (jump, call, return)	Malvino Ch10,11 (partially)
13	Dual Inline Packaged and Surface Mount Device (SMD) Integrated Circuits, Introduction to System Integration and Printed Circuit Board design, Memories: classification and architecture, RAM memory cells, Read only memory	Lecture Slides Harris 5.5

Textbooks

[Harris] Digital Design and Computer Architecture ARM Edition
[Brown] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design” 3rd Edition, McGraw Hill (2014)
[Floyd] Thomas L. Floyd, “Digital Fundamentals” 11th Edition, Pearson (2015)
[Mano] Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL” 5th Edition, Pearson (2013)
[Malvino] Albert P. Malvino, Jerald A. Brown - Digital Computer Electronics-McGraw-Hill (1993)

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

EEE 304 (Jan 2024)

Mon, 01 Jan 2024 00:00:00 +0000

EEE 304 - Digital Electronics Laboratory

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

Course Outline

Delivery Topic

Week 01 - Lecture on Introduction to overview of the experiments and projects, Lab Policies, Grading; formation of Teams for design project and lab works
Week 02 - Experiment 01 Introduction To Basic Gates and Logic Simplification Techniques with discrete logic and Schematic Capture
Week 03 - Experiment 02 Design, Simulation, and Implementation of Arithmetic Circuits using 74 series ICs and VerilogHDL
Week 04 - Project Proposal Presentation Describe specific technical requirements to be attained during the project
Week 05 - Experiment 03 Design, Simulation, and Implementation of Combinational Circuits: Decoder/Encoder/Multiplexer Circuit using 74 series ICs and Verilog HDL
Week 06 - Experiment 04 Design, Simulation, and Test of Sequential Circuits Using Verilog and Implementation In FPGA
Week 07 - Project Design Presentation Present/demonstrate the technical progress of the project. Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project
Week 08 - Experiment 05 Design, Simulation and Test of Finite State Machines Using Verilog And Implementation In FPGA.
Week 09 - Experiment 06 Design, Simulation and Test of an SAP computer Using Verilog And Implementation In FPGA.
Week 10 - Project Progress Presentation Present/demonstrate the technical progress of the project. Describe any necessary modification proposed to address public health and safety, cultural, societal, and environmental considerations related to the project
Week 11 - Lab Test Lab Test performed on Experiment 1-6
Week 12 - Peer Assessment and Viva - Present/demonstrate the technical progress, team and individual contribution and ethical principles applied to the design and implementation of the project, Answer Technical Questions related to the project Individually and ethical principles applied to the design and implementation of the project
Week 13 - Project Demonstration - Use multimedia and necessary documentation user manual, video demonstration and project report to clearly communicate the project

Course Outcome

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<br/>
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Statement</font></font></p>
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">ding</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Taxonomy</font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.08in"><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">level(s)**</font></font></p>
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Method(s)
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Activity(-ies)</font></font></p>
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</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">gates</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">in</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">breadboards</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(a)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.31in; margin-right: 0.31in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">P3</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.26in; margin-right: 0.2in; text-indent: -0.04in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Labwork</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Labtest</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.24in; margin-right: 0.07in; text-indent: -0.15in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab
Performance</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab
Test</font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.4in"><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Quiz</font></font></p>
</td>
</tr>
<tr valign="top">
<td width="22" height="55" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.06in; margin-right: 0.05in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO2</font></font></p>
</td>
<td width="222" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-right: 0.08in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>Construct
</b></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Verilog
programs and logic</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">circuits</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">for</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">solving</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">problems</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">related</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">to</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">digital</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">electronics,
understanding the practical</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">limitations</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(e)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.31in; margin-right: 0.31in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">P5</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.26in; margin-right: 0.2in; text-indent: -0.04in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Labwork</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Labtest</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.24in; margin-right: 0.07in; text-indent: -0.15in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab
Performance</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Lab
Test</font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.16in; margin-right: 0.15in; text-indent: 0.24in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Quiz</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Project</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.6pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font></p>
</td>
</tr>
<tr valign="top">
<td width="22" height="41" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.06in; margin-right: 0.05in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO3</font></font></p>
</td>
<td width="222" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="justify" style="orphans: 0; widows: 0; margin-left: 0.07in; margin-right: 0.27in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>design
</b></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">a
digital system to solve a relevant</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">problem
with due considerations to public</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">health</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">and
safety,</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">societal,
cultural</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">and</font></font></p>
<p align="justify" style="orphans: 0; widows: 0; margin-left: 0.07in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">environmental</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">consideration</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(c)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.33in"><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">P7</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.39in; margin-right: 0.38in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">--</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.13in; margin-right: 0.13in; text-indent: -0in; margin-top: 0.06in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Project</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Demonstration,</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Project</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font></p>
</td>
</tr>
<tr valign="top">
<td width="22" height="27" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.06in; margin-right: 0.05in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO4</font></font></p>
</td>
<td width="222" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-right: 0.08in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>demonstrate
</b></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">application
of ethical principles</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">and
practices</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">in</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">the</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">project,
and</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>evaluate</b></font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">peer</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">team</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.2pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">members</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">ethically</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(h)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.32in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">A3</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.39in; margin-right: 0.38in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">--</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.35in; margin-right: 0.1in; text-indent: -0.23in; margin-top: 0.07in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Peer
evaluation,</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font></p>
</td>
</tr>
<tr valign="top">
<td width="22" height="27" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.06in; margin-right: 0.05in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO5</font></font></p>
</td>
<td width="222" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-right: 0.26in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>work
</b></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">effectively
as an individual and as a</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">team</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">member
towards</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">the</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">successful</font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">completion</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">of</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">the</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">project</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(i)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.33in"><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">P4</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.39in; margin-right: 0.38in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">--</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.26in; margin-right: 0.24in; text-indent: -0.01in; margin-top: 0.07in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Viva,
Peer</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">evaluation</font></font></p>
</td>
</tr>
<tr valign="top">
<td width="22" height="26" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.06in; margin-right: 0.05in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO6</font></font></p>
</td>
<td width="222" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-right: 0.31in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><b>report
</b></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">effectively
on the design done for</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -2.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">CO3</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">with</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">presentation,</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">user-manual
and</font></font></p>
<p style="orphans: 0; widows: 0; margin-left: 0.07in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">detailed
report</font></font></p>
</td>
<td width="53" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.18in; margin-right: 0.18in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">PO(j)</font></font></p>
</td>
<td width="62" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p style="orphans: 0; widows: 0; margin-left: 0.32in"><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">A3</font></font></p>
</td>
<td width="71" style="border: 1px solid #000000; padding: 0in 0.08in"><p style="orphans: 0; widows: 0; margin-top: 0.01in; margin-bottom: 0in">
<br/>
</p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.39in; margin-right: 0.38in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">--</font></font></p>
</td>
<td width="86" style="border: 1px solid #000000; padding: 0in 0.08in"><p align="center" style="orphans: 0; widows: 0; margin-left: 0.15in; margin-right: 0.14in; margin-bottom: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Video</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: 0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Presentation</font></font></p>
<p align="center" style="orphans: 0; widows: 0; margin-left: 0.15in; margin-right: 0.14in; margin-top: 0in">
<font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Project</font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt"><span style="letter-spacing: -0.1pt">
</span></font></font><font face="Times New Roman, serif"><font size="2" style="font-size: 9pt">Report</font></font></p>
</td>
</tr>

EEE 415 (Jan 2025)

Mon, 01 Jan 2024 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team EEE 415 A (Jan 2025).

Offered to

L4-T1 Section B1 and B2 (2021 Intake)

Syllabus (as approved in 2022)

Grading Policy

Class Attendance (10%) – Class participation and attendance will be recorded in every class. 30 Marks as per university AC policy
Continuous Assessment (20%) – 1 assignment (20) – Mandatory 3 Class tests, best 2 counted (40)
Final Examination (70%)– A comprehensive term final examination will be held at the end of the Term following the guideline of the Academic Council

Weekly Schedule

As per the routine published in the Department of EEE website.

Textbooks

[Harris] Sarah Harris, David Harris – “Digital Design and Computer Architecture, ARM Edition, Morgan Kaufmann (2015) - Chapter 6,7,8

[Patterson] David A. Patterson and John L. Hennessy, “Computer Organization and Design – The Hardware / Software Interface ARM edition” Morgan Kaufmann - Chapter 1

[Zhu] Yifeng Zhu “Embedded Systems with ARM Cortex-M Microcontrollers with Assembly Language and C”

Semester Plan

Week	Lectures	Topic	Textbook
1	1-3	Fundamentals of microprocessor and computer design, processor data path, architecture, microarchitecture, introduction to CISC and RISC, complexity, metrics, and benchmark.	Patterson 1
2	4-6	Assembly Language.	Harris 6.1-6.3
3	7-9	Assembly Language Programming.	Harris 6.3
4	10-12	Machine Language, Compiling, Assembling.	Harris 6.4
5	13-15	Performance Analysis, Single Cycle and Multicycle Processor.	Harris 7.1-7.4
6	16-18	Pipelining, Hazards, Advanced Microarchitecture.	Harris 7.5,7.7
7	19-21	Memory Systems – Cache and Virtual Memory.	Harris 8.2-8.4
8	20-24	Introducing Embedded System Design, IoT, Arm Cortex m4.	Lecture Slides
9	25-27	General Purpose Input Output.	Zhu 14
10	28-30	General Purpose Timers.	Zhu 15.1-15.3
11	31-33	Interrupts.	Zhu 11, 15.4
12	34-36	ADC + DAC.	Zhu 20,21
13	37-39	Serial Communication.	Zhu 22

EEE 415 (July 2023)

Mon, 01 Jan 2024 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team “EEE 415 C (July 2023)”.

Introduction

The syllabus of this course has been changed and the course has been completely redesigned from grounds up.

Syllabus (as approved in 2022)

Grading Policy

Class Attendance (10%) – Class participation and attendance will be recorded in every class. 30 Marks as per university AC policy
Continuous Assessment (20%) – 1 assignment (20) – Mandatory 3 Class tests, best 2 counted (40)
Final Examination (70%)– A comprehensive term final examination will be held at the end of the Term following the guideline of the Academic Council

Weekly Schedule

As per the routine published in the Department of EEE website.

Textbooks

[Harris] Sarah Harris, David Harris – “Digital Design and Computer Architecture, ARM Edition, Morgan Kaufmann (2015) - Chapter 6,7,8

[Patterson] David A. Patterson and John L. Hennessy, “Computer Organization and Design – The Hardware / Software Interface ARM edition” Morgan Kaufmann - Chapter 1

[Zhu] Yifeng Zhu “Embedded Systems with ARM Cortex-M Microcontrollers with Assembly Language and C”

Semester Plan

Week	Lectures	Topic	Textbook
1	1-3	Fundamentals of microprocessor and computer design, processor data path, architecture, microarchitecture, introduction to CISC and RISC, complexity, metrics, and benchmark.	Patterson 1
2	4-6	Assembly Language.	Harris 6.1-6.3
3	7-9	Assembly Language Programming.	Harris 6.3
4	10-12	Machine Language, Compiling, Assembling.	Harris 6.4
5	13-15	Performance Analysis, Single Cycle and Multicycle Processor.	Harris 7.1-7.4
6	16-18	Pipelining, Hazards, Advanced Microarchitecture.	Harris 7.5,7.7
7	19-21	Memory Systems – Cache and Virtual Memory.	Harris 8.2-8.4
8	20-24	Introducing Embedded System Design, IoT, Arm Cortex m4.	Lecture Slides
9	25-27	General Purpose Input Output.	Zhu 14
10	28-30	General Purpose Timers.	Zhu 15.1-15.3
11	31-33	Interrupts.	Zhu 11, 15.4
12	34-36	ADC + DAC.	Zhu 20,21
13	37-39	Serial Communication.	Zhu 22

EEE 416 (Jan 2025)

Mon, 01 Jan 2024 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team. EEE 416 B1 and B2 (Jan 2025)

Offered to

L4-T1 Section B1 and B2 (2021 Intake)

Syllabus

EEE 416

EEE 415

Course Objectives

To perform experiments in relevance with the theoretical concepts of the course EEE 415: Microprocessor and Embedded Systems
To conduct design projects in order achieve specific program outcomes described in the Course Outline

Course Outcomes

Upon successful completion of the course, students will be able to

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Utilize VerilogHDL, ARM assembly, C programming and microcontrollers boards for implementing and analyzing theoretical concepts at software and hardware levels	PO(e)	P4, C4	–	Lab Performance, Lab Test, Quiz, Viva, Project
CO2	Design an embedded system with appropriate considerations to safety, cultural, societal, and environmental considerations	PO(c)	C6	–	Project Report and Hardware demonstration
CO3	Assess impact of embedded systems project design on Societal, Health, Safety, Legal and Cultural Issues	PO(f)	C5	–	Presentation and Report
CO4	Evaluate Sustainability the and Impact of the Designed embedded systems Project in the Societal and Environmental Contexts	PO(g)	C5	–	Presentation and Report
CO5	Demonstrate membership and leadership in designing embedded system related problem solving	PO(i)	P7	–	Project logbook , Peer assessment, Viva, Presentation
CO6	Communicate effectively on embedded system related design with presentation and detailed report	PO(j)	A2	–	Video Presentation, Design Report
CO7	Demonstrate project management and cost analysis for embedded system project	PO(k)	A3	–	Project Report and Presentation

For details of program outcome (PO) statements, please see the departmental website or course curriculum _

KPA Mapping

Weekly Plan

Week	Mode	Topic
1	Experiment 00	Introduction to Lab, Lab Policies and Tools
2	Experiment 01	Arm Cortex M: GPIO: Interfacing LED, Push-Button and Stepper Motor	CO1 (PO(e))
3	Experiment 02	Arm Cortex M: Interrupt and Timers I	CO1 (PO(e))
4	Experiment 03	Arm Cortex M: Interrupt and Timers II	CO1 (PO(e))
5	Presentation	· Project Proposal Presentation · Describe specific technical requirements to be attained during the project · Describe sustainability and impact of the work in societal and environmental contexts	CO4 (PO(g))
6	Experiment 04	Arm Cortex M: Analog Interfacing	CO1 (PO(e))
7	Experiment 05	Arm Assembly Language and Architecture	CO1 (PO(e))
8	Experiment 06	Arm Micro Architecture: Single Cycle, Multi Cycle and Pipelining	CO1 (PO(e))
9	Project Progress Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-1 · Present/demonstrate the technical progress of the project · Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project	CO2 (PO(c)) CO4 (PO(f))
10	Assessment	Lab Test	CO1 (PO(e))
12	Lab Quiz and Viva	Sessional Quiz	CO1 (PO(e)) CO2 (PO(c))
11	Project Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-2 · Present/demonstrate the technical progress of the project · Describe multidisciplinary aspects of the project · Describe how each team member has been effectively working (individually and as a member or leader) to attain the goals (Self- and peer-assessment of students)	CO5 (PO(c) CO7 (PO(i))
13	Final Presentation	· Describe how engineering management principles and economic decision-making applied to the project · Use multimedia and necessary documentation (user manual, video demonstration and project report) to clearly communicate the project	CO7 (PO(k)) CO6 (PO(j))
14	Project Demonstration	· Practical demonstration of the project: show evidence that specific technical requirements have been attained by the project	CO2 (PO(c))

Distribution of Marks

Class Participation and Attendance 10%
Lab Reports 5%
Lab Experiments 10%
Lab Test 15%
Sessional Quiz 15%
Final Project 45%
Total 100%

Lab Usage Policy

No Food or Drink is allowed in the laboratory.
At the beginning of each lab, please check out the “Embedded Systems Kit” box from Mr. Selim, writing your name and information in logbook. Please check individually if each component is in the box.
Report any missing parts at the beginning of the lab.
You will be financially responsible for unreported missing items
Do not separate / tear the jumper cable collection.
Before connecting the USB port, double check the power and ground connection of your externally connected components.

EEE 416 (July 2023)

Mon, 01 Jan 2024 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team.

2023Introduction

In the 2023 syllabus the 416 course will be heavily project focused. We will use the project of EEE 416 as a primary replacement of the Capstone Project, for culmination of program outcomes.

Syllabus

EEE 416

EEE 415

Course Objectives

To perform experiments in relevance with the theoretical concepts of the course EEE 415: Microprocessor and Embedded Systems
To conduct design projects in order achieve specific program outcomes described in the Course Outline

Course Outcomes

Upon successful completion of the course, students will be able to

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Utilize VerilogHDL, ARM assembly, C programming and microcontrollers boards for implementing and analyzing theoretical concepts at software and hardware levels	PO(e)	P4, C4	–	Lab Performance, Lab Test, Quiz, Viva, Project
CO2	Design an embedded system with appropriate considerations to safety, cultural, societal, and environmental considerations	PO(c)	C6	–	Project Report and Hardware demonstration
CO3	Assess impact of embedded systems project design on Societal, Health, Safety, Legal and Cultural Issues	PO(f)	C5	–	Presentation and Report
CO4	Evaluate Sustainability the and Impact of the Designed embedded systems Project in the Societal and Environmental Contexts	PO(g)	C5	–	Presentation and Report
CO5	Demonstrate membership and leadership in designing embedded system related problem solving	PO(i)	P7	–	Project logbook , Peer assessment, Viva, Presentation
CO6	Communicate effectively on embedded system related design with presentation and detailed report	PO(j)	A2	–	Video Presentation, Design Report
CO7	Demonstrate project management and cost analysis for embedded system project	PO(k)	A3	–	Project Report and Presentation

For details of program outcome (PO) statements, please see the departmental website or course curriculum _

KPA Mapping

Weekly Plan

Week	Mode	Topic
1	Experiment 00	Introduction to Lab, Lab Policies and Tools
2	Experiment 01	Arm Cortex M: GPIO: Interfacing LED, Push-Button and Stepper Motor	CO1 (PO(e))
3	Experiment 02	Arm Cortex M: Interrupt and Timers I	CO1 (PO(e))
4	Experiment 03	Arm Cortex M: Interrupt and Timers II	CO1 (PO(e))
5	Presentation	· Project Proposal Presentation · Describe specific technical requirements to be attained during the project · Describe sustainability and impact of the work in societal and environmental contexts	CO4 (PO(g))
6	Experiment 04	Arm Cortex M: Analog Interfacing	CO1 (PO(e))
7	Experiment 05	Arm Assembly Language and Architecture	CO1 (PO(e))
8	Experiment 06	Arm Micro Architecture: Single Cycle, Multi Cycle and Pipelining	CO1 (PO(e))
9	Project Progress Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-1 · Present/demonstrate the technical progress of the project · Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project	CO2 (PO(c)) CO4 (PO(f))
10	Assessment	Lab Test	CO1 (PO(e))
12	Lab Quiz and Viva	Sessional Quiz	CO1 (PO(e)) CO2 (PO(c))
11	Project Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-2 · Present/demonstrate the technical progress of the project · Describe multidisciplinary aspects of the project · Describe how each team member has been effectively working (individually and as a member or leader) to attain the goals (Self- and peer-assessment of students)	CO5 (PO(c) CO7 (PO(i))
13	Final Presentation	· Describe how engineering management principles and economic decision-making applied to the project · Use multimedia and necessary documentation (user manual, video demonstration and project report) to clearly communicate the project	CO7 (PO(k)) CO6 (PO(j))
14	Project Demonstration	· Practical demonstration of the project: show evidence that specific technical requirements have been attained by the project	CO2 (PO(c))

Distribution of Marks

Class Participation and Attendance 10%
Lab Reports 5%
Lab Experiments 10%
Lab Test 15%
Sessional Quiz 15%
Final Project 45%
Total 100%

Lab Usage Policy

No Food or Drink is allowed in the laboratory.
At the beginning of each lab, please check out the “Embedded Systems Kit” box from Mr. Selim, writing your name and information in logbook. Please check individually if each component is in the box.
Report any missing parts at the beginning of the lab.
You will be financially responsible for unreported missing items
Do not separate / tear the jumper cable collection.
Before connecting the USB port, double check the power and ground connection of your externally connected components.

Gesture Controlled Bot with Temperature & Humidity (TH) Sensing Features

Mon, 01 Jan 2024 00:00:00 +0000

Sb2S3/AlGaAs based Reconfigurable Metasurface for Dynamic Polarization and Directionality Control of Quantum Emitter Emission

Mon, 01 Jan 2024 00:00:00 +0000

VO₂-Based All-Optical Reflection Modulator Published

Mon, 01 Jan 2024 00:00:00 +0000

The proceedings from the International Photonic Conference in Florida, USA, include a paper titled “VO₂-Based All-Optical Reflection Modulator for 2 μm Wave Band.” The study explores the use of vanadium dioxide (VO₂) in developing optical modulators operating at the 2 μm wavelength, offering insights into the design of efficient optical communication components.

BME 6103 (BME) Biophotonics (October 2023)

Sun, 01 Oct 2023 00:00:00 +0000

Welcome

Welcome to the course on BME 6103 Biophotonics. This course is offered to the Post Graduate Students of the Dept of BME, BUET. We are taking classes through Google Classroom and all communications for this course will be done through the class team of the course. This webpage will not be updated, and kept just for prospective students to have an idea about the course.

Class Schedule

Saturday 11am-1pm Room BME 1108, ECE Building, BUET

Syllabus

Course Content

Fundamentals of biophotonics: diverse applications, biophotonics spectral windows, light absorption, signal attenuation, emerging biomedical optical technologies, motivation for optical imaging; Behavior of light in biological tissue: physics of light-matter interaction, absorption, scattering, polarization and fluorescence. Optical fibers for biophotonic applications: overview of optical fibers, double-clad fibers, hard-clad silica fibers, biomedical applications; Light sources: radiometry, arc lamps, light-emitting diodes, lasers for biophotonics, superluminescent diodes; Optical detectors: the pin photodetector, avalanche photodiodes, multichannel detectors, photomultiplier tubes, optical couplers and circulators; Optical probes and biosensors: optical fiber probe, optical sensors, interferometric sensors, photonic crystal fiber biosensors, surface plasmon resonance biosensor. Spectroscopic methodologies: fluorescence spectroscopy, FRET/FLIM, fluorescence correlation spectroscopy, elastic scattering spectroscopy, diffuse correlation spectroscopy; Application of biophotonic instrumentation.

Textbooks

[Keiser] Biophotonics: Concepts to Applications 2nd Edition (2022) by Gerd Keiser Required to have a printed copy. Will be used in open book term final exam

Reference book [Prashad] Introduction to Biophotonics by Paras N. Prasad

[Tsia] Understanding Biophotonics: Fundamentals, Advances and Applications edited by Kevin K. Tsia

Learning Outcomes (LO)

On successful completion of this course unit, students should be able to:

Understand the Nano systems and Devices.
Become Advances in Device Technology.
Analyze the Nano Electro Mechanical Systems.
Demonstrate the bio functionality on silicon.

Teaching-learning Strategy

Class lectures, Case studies, Research papers review, Practical problem solution etc.

Grading Policy

Class Test- 20% (3 class tests, all class tests counted.)
Midterm Presentation - 30% (15 minutes presentation and Q A by the students on a relevant paper.)
Final Examination - 50% (Primarily focus on very basic concepts of the course and class discussions)

EECE 6609 (MIST) Nano Systems (October 2023)

Sun, 01 Oct 2023 00:00:00 +0000

Welcome

Welcome to the course on EECE 6609 Nano Systems. This course is offered to the Post Graduate Students of the Dept of EECE of the Military Institute of Science and Technology, with permissiion from the BUET authorities. We are taking classes through Google Classroom and all communications for this course will be done through the class team of the course. This webpage will not be updated, and kept just for prospective students to have an idea about the course.

Class Schedule

Saturday 3pm-6pm Room EECE 701, Tower 3, MIST

Background

This course is a first year graduate level course for students who are interested in doing research on Nano Systems and Nano Technology and their great wonders.

As a graduate level course, we would focus on active learning in the course, where you will participate in group project to grasp the concepts and learn about the vast field. The course will be really useful if you are thinking about pursuing research in Nanophotonics, or want to know more about the field.

Syllabus

Course Content

Nanosystems and Devices: Introduction- nanomaterials, nanodevices, nanostructures. Nanoscale Lithography: X-ray, Electron-Beam and Ion-Beam; Soft Lithography; Scanning Probe Lithography. Advances in Device Technology: nanoscale silicon devices, process technology, present challenges. Self Assembled Nanocrystals: self assembly, surface defects and passivation, structures, energy levels, transitions, luminescence and lasing. Nano Electro Mechanical Systems (NEMS): stress in thin films, mechanical to electrical transduction, surface engineering techniques, process flow, NEMS actuators, high aspect ratio system technology. Nano Biotechnology: scope and dimensions; detection of biological species on electrical, mechanical and optical criteria; Bio functionality on silicon; Biochip sensors and systems- structures, process technology.

Learning Outcomes (LO)

On successful completion of this course unit, students should be able to:

Understand the Nano systems and Devices.
Become Advances in Device Technology.
Analyze the Nano Electro Mechanical Systems.
Demonstrate the bio functionality on silicon.

Teaching-learning Strategy

Class lectures, Case studies, Research papers review, Practical problem solution etc.

Grading Policy

Final Review Papaer - 40%
Final presentaation - 10%
Final Examination - 50%

Expectation

It would be expected that by the end of the course, you are able to do a comprehensive review on a particular topic of interest and are able to effectively communicate it orally. Regular participation in class discussion is strongly encouraged. Although, preparing the class presentations and report would demand time and effort, hopefully, by successful completion of the work, you would have a publishable work, and we can discuss after the end of the semester if we can compile and publish the work.

It is expected that students sign an honour pledge for the class and refrain from plagiarising. All reports would be checked with turnitin plagiarism checker and any plagiarized work would be dealt with a “F” grade in the entire course.

Detailed Grading Policy

Final Project + Presentation (40%)

For Final Project, you must do an original comprehensive literature review on a particular topic relevant to the course and write a minimum 1600 word Review Article on it, with at least 35 literature references.

Scope of write up (including but not limited to):

Broad introduction of the field
Present Challenges
Fabrication methods
Breakthrough publications
Significant applications

Instruction:

You need to form groups of * students. Each group will work on a particular scope. I will circulate a google form where you can give choice regarding the topics. Each group’s broad topic should be unique.

Once you choose broad the topic, you need to do choose a special topic from it (as for example, from Nanophotonic systems a special topic can be imaging with metasurface). Your subtopic should be unique in a sense that there is no other review paper on the particular subtopic. Prepare a short outline of the paper (Introduction, Conclusion, which topics you will be covering etc) do a literature search on the topic and create an outline of your paper. Deadline to submit the outline is 2 weeks.

After I okay the outline, you need to do further literature search and form your review on the topic. You are expected to write a publishable review on the topic. Here are some resources that might help you in the process:

To improve writing skill, I highly recommend the Kristin Sainani’s course from Stanford University, . Complete week 1-5 of the course to improve your writing style.

Originality of work: The paper that you write must be an original work of your own writing. The goal of the assignment is for you to learn writing a review. The papers will be checked with plagiarism checking software. Any similarity with already published work will result in a failure (F) in the assignment. Read this article on

If you choose to do so, I am willing to work on the final paper further with the possibility of publishing it in a peer-reviewed journal. This will be done after completion of the grading of the course to avoid any bias on grades.

Review Article LaTeX Template

The following overleaf project is exclusively made for this project. You MUST use this template to format the final submission of your project. . Please note that the individual contribution of each section must be clearly marked with the \contributingauthor{} macro

Review Article Grading Criteria and Rubric

Title and Introduction (10 points)

Clarity and Relevance (3 points): Is the title clear and does it reflect the topic’s relevance to the course? Is the introduction engaging and informative?
Scope and Significance (3 points): Does the introduction clearly define the scope of the review article and its significance in the context of the course?
Thesis Statement (4 points): Is there a well-defined thesis statement that sets the direction for the review?

Literature Review (40 points)

Comprehensiveness (15 points): Does the literature review include a comprehensive collection of relevant sources (30-50 references)? Is the selection of sources well-justified?
Synthesis and Analysis (15 points): Does the review demonstrate the ability to synthesize and critically analyze the selected literature? Are key findings and trends identified?
Integration with Course Content (10 points): How effectively does the literature review integrate with the course content? Does it contribute to the course’s learning objectives?

Summary Figures and Tables (10 points)

Summary Figure (5 points): Is there a clear and informative summary figure that visually represents the key findings or concepts discussed in the review?
Summary Table (5 points): Is there an organized and concise summary table that highlights important details from the reviewed literature?

Organization and Clarity (15 points)

Structure (5 points): Is the article well-organized with clear sections (e.g., introduction, literature review, discussion)? Is there a logical flow of ideas?
Clarity of Expression (5 points): Is the writing clear, concise, and free from jargon? Are technical terms explained where necessary?
Transitions (5 points): Are there smooth transitions between paragraphs and sections, making it easy for the reader to follow the argument?

Quality of Figures (10 points)

Clarity and Relevance (5 points): Are the figures clear, relevant, and effectively used to support the content of the review?
Originality and Creativity (5 points): Do the figures demonstrate originality and creativity in visually presenting information?

Individual Contribution (25 points)

Contributions (15 points): Each team member’s individual contributions are clearly identified within the text. Each student’s contribution should align with their respective responsibilities.
Quality of Contribution (10 points): The individual contributions should demonstrate depth and relevance to the overall review.

Conclusion and Recommendations (10 points)

Summary (5 points): Does the conclusion effectively summarize the key findings and insights from the literature review?
Recommendations (5 points): Are there clear recommendations or implications based on the review’s findings?

References and Citations (10 points)

Accuracy (5 points): Are citations and references consistently formatted following a recognized citation style (e.g., APA, IEEE)? Are all sources properly credited?
Relevance (5 points): Are all references relevant to the topic, and do they contribute to the overall quality of the review?

Overall Quality (30 points)

Originality and Depth (10 points): Does the review exhibit original thought and in-depth analysis? Does it go beyond summarizing existing knowledge?
Engagement (10 points): Does the review article engage the reader and maintain their interest throughout?
Formatting and Aesthetics (10 points): Is the article properly formatted in the given LaTeX template and aesthetically pleasing?

Total (150 points)

Group Contribution (50 points): Assess group collaboration and whether each member fulfilled their roles and responsibilities.
Individual Contribution (25 points): Evaluate individual contributions based on the clarity and quality of each student’s work within the article.
Content and Elements (75 points): Assess the quality and completeness of the review article, including figures, tables, organization, and clarity.

Grading Scale:

135-150 points: Excellent
120-134 points: Very Good
105-119 points: Good
90-104 points: Fair
Below 90 points: Needs Improvement

Excel Hacks

Fri, 07 Jul 2023 00:00:00 +0000

The more senior one gets, probably more useful Word and Excel becomes. It is helpful to quickly search Google to find a correct answer to a problem, but sometimes the first result points to a StackOverflow thread where someone simply says “Why don’t you google it?”. So, I am posting this blog article to make life easy for me (as well as whoever stumbles onto my website). It would be some helpful macros and functions that I find useful. Some of the functions should also work with Google Sheets without modification.

Bangladeshi Taka in Lakh and Crore in Excel

It is super annoying to see number formatted in Millions and Billions, where realistically, Lakh and Crore is more meaningful to Bangladeshi (and probably Indian) people. It is amazing that Microsoft does not have a default numbering format for us. Anyway, to get properly formatted lakh and excel formats, Go to the ribbon Home>Number>More Number Formats>Custom

Enter any of the following formats as suitable:

Positive Number only with paisa (1,15,000.00):

[>9999999]##\,##\,##\,##0.00;[>99999]##\,##\,##0.00;##,##0.00

Positive Number only ignoring paisa (1,15,000):

[>9999999]##\,##\,##\,##0;[>99999]##\,##\,##0;##,##0

Shamima Akter Mitu Defends Master's Thesis

Wed, 03 May 2023 00:00:00 +0000

Congratulations to Shamima Akter Mitu for successfully defending her Master’s thesis. This achievement signifies her dedication and contribution to her area of research, marking a milestone in her academic career.

Reconfigurable Broadband Metasurface Published

Sat, 29 Apr 2023 00:00:00 +0000

A paper titled “Reconfigurable Broadband Metasurface with Switchable Functionalities in the Visible Range” has been published in Optical Materials Express. The research presents a metasurface capable of switching functionalities across the visible spectrum, enabling dynamic control over light manipulation for applications in imaging and display technologies.

AI Tools to Make an Academic's Life Easy

Mon, 24 Apr 2023 00:00:00 +0000

2023 is probably the year of Artificial Intelligence. Though AI was working in the background to imrpove search suggestions and images, ChatGPT truly showed us the power of AI and how it can reshape our future. Though the sinister undertone of getting replaced by AI, or the possibility of making human race dumber looms in the horizon, AI is here to stay. Probably library work, critical thinking, research, manuscript writing - everything will be delegated to AI in the future, and academia will drastically shrink. Those who remain in the academia must adapt to use the AI tools of the future. Here is a nice list of AI tools especially for an academic (Courtesy . It is difficult to say how many of the tools will survive once the AI bubble bursts and we start to see more giant AI companies absorbing and acquiring the small ones. I wish more decentralized and stand alone AI apps were available.

For Writing:

A personal writing assistant that will make sure you never face the writer’s block

An editor to help you polish your academic writing. Also has an MS Word plugin so you can edit from within MS Word.

For Reading:

A persona reading assistant that creates summaries of research papers with unfamiliar terms hyperlinked to Wikipedia entries.

ChatGPT for research papers. Upload a paper and start asking it questions.

A Chrome extension that summarizes research papers within your browser. Also helps you brainstorm ideas.

One of the most powerful and versatile tools currently available for reading journal articles. You can ask your reading Copilot to explain difficult passages.

For taking notes:

Lateral

A unique app that helps you find common themes across multiple research papers — in minutes. Lateral (lateral.io) is no longer online.

Not an AI-powered app but still much better than many available tools. I am using it for my current research project. Helps you visualize connections between different ideas and concepts. Also lets you export your notes to an MS Word file.

Think of it as Twitter but for note-takers. Take notes on research papers and share them with likeminded people across the world

Converts your voice notes into coherent and cohesive prose.

Search engines:

Unlike ChatGPT that gives you fake citations, Consensus answers your questions with references to actually published papers.

Answers your clinical questions with citations to published papers.

A search engine to help you find the most suitable database for your research.

Including Images in Markdown

Fri, 14 Apr 2023 00:00:00 +0000

Both the websites that I manage, the Department of EEE website and my personal website uses markdown formatting. It is possible to use images in jpeg or png format, but it is much easier to use inline description of an image. Here is a workflow that I found to be helpful. If you have a complicated table in word, you can easily include it inline in vector format

Steps

Keep your table / art in word document, remove all other text, and click Save As and save the file as PDF.
Open the PDF file in Adobe Illustrator or InkScape. Remove any unnecessary white boxes. Then save the file as SVG
Open the SVG file in notepad. Copy the text and paste it in MarkDown.

Example Table:

EEE 6505 Nanophotonics and Plasmonics (April 2023)

Sat, 01 Apr 2023 00:00:00 +0000

Welcome

Welcome to the course on EEE 6505 Nanophotonics and Plasmonics. We are taking classes through Microsoft Teams and all communications for this course will be done through the class team of the course. This webpage will not be updated, and kept just for prospective students to have an idea about the course.

Class Schedule

Saturday 8am-11am Room EEE 625

2023 Notices

We will have our first lecture on 08/07/2023 Saturday 8am. Please come to the class by 7:55 am, as we need to free up the room at exactly 10:30 am.
Classes will be held offline with live lectures. Your physical presence will be needed for the class.
** In this year, the review article for final project should be of publishable quality to ensure that you receive the highest grade. **
If you are retaking the course due to an I grade or a grade improvement, you must separately participate all assessments. Marks from previous year’s course will not carry forward.

Background

I completed my PhD from Purdue University in Summer of 2019. I had acquired knowledge on modelling, fabricating and characterizing plasmonic metasurfaces for my PhD work, creating the thinnest color hologram with epitaxial silver based metasurface at the time of publication. I am really grateful to my supervisor Prof. Alexandra Boltasseva for introducing me to the area, and my mentor, Prof. Vladimir Shalaev for introducing me to the area of nanophotonics through his course in Purdue. This course is heavily influenced by Prof. Shalaev’s course (freely available on Nanohub), which I attended as a first year graduate student in Purdue.

This course would introduce graduate students to the field of Nanophotonics and its great wonders. We will talk about light-matter interaction in the nano-scale, how to make devices that goes beyond the diffraction limit, their theory, application and design.

As a graduate level course, we would focus on active learning in the course, where you will participate in group projects and individual assignments to grasp the concepts and learn about the vast field. The course will be really useful if you are thinking about pursuing research in Nanophotonics, or want to know more about the field.

Syllabus

Interaction of light with material; wave equation in matter from Maxwell’s equations; Dielectric properties of insulators, semiconductors and metals; Interaction of light with microstructures and nanostructures; Optical properties of metal-dielectric composites; Photonic Crystals: Electromagnetic effects in periodic media; One-, two- and three-dimensional photonic crystals; Applications of photonic crystals: omni-directional reflection, light localization, photonic crystal fibers; Surface Plasmons: Surface plasmon polariton at single interface, multilayer system, localized surface plasmons; Excitation of surface plasmon polariton; Prism coupling, grating coupling; Application of surface plasmons; Sub-wavelength waveguides, plasmonic photovoltaics, plasmonic bio-sensors; Metamaterials: Electric metamaterials, magnetic metamaterials, negative index metamaterials, hyperbolic metamaterials.

Suggested Text Books

John D. Joannopoulos, Steven G. Johnson, Joshua N. Winn, and Robert D. Meade, Photonic Crystals: Molding the Flow of Light second edition (Princeton Press, Freely available at )
Stephen A Maier, Plasmonics: Fundamentals and Applications,
Wenshan Cai, Vladimir Shalaev, Optical Metamaterials: Fundamentals and Applications,

Lesson Plan

(Subject to change based on student interest and class discussion)

08 Jul 2023 - Week 01 – Introduction

15 Jul 2023 - Week 02 – Light-Matter Interaction I

22 Jul 2023 - Week 03 – Light-Matter Interaction II

29 Jul 2023 - Week 04 – Discussion on Mid Term Presentation and Final Project

05 Aug 2023 - Week 05 – Photonic Crystals I

12 Aug 2023 - Week 06 – Photonic Crystals II

19 Aug 2023 - Week 07 – Mid Term Presentation I

26 Aug 2023 - Week 08 – Mid Term Presentation II

02 Sep 2023 - Week 09 – Metal Optics I

09 Sep 2023 - Week 10 – Metal Optics II

16 Sep 2023 - Week 11 – Applications of Plasmonics

23 Sep 2023 - Week 12 – Metamaterials

30 Sep 2023 - Week 13 – Final Project - I

07 Oct 2023 - Week 14 – Final Project - II

Grading Policy

Midterm Presentation - 25%
Final Project + Presentation - 40%
Class Tests - 10%
Final Examination - 25%

Incomplete Grade Policy

In this course, you will be given an I grade, ONLY if you complete the midterm and final presentation, and just fail to appear in the final exam due to reasons beyond your control. You must apply to Head of the Department within 1 week of commencement of the final exam. Failure to participate either the midterm or final projects would not be considered for I grade, and your grading would be done through the Grading criteria. Not participating in midterm or final project, as well as being absent in Final Exam will result in an F grade, regardless of the circumstances.

Expectation

Detailed Grading Policy

Class Test (10%)

There will be 4 class tests on the 4 broad topics of the course. Best 3 will be counted for 10% of the grade.

Midterm Presentation (25%)

Each student 10 minute offline/live presentation and 5 minutes question answer (points will be deducted for more than 12 minutes presentation) All students must attend the talks and participate in question answering.

Grading Rubric:

Peer Grading (30)
Instructor Grading (30)
Active Participation (30)
Punctuality (10)

Final Project + Presentation (40%)

Scope of write up (including but not limited to):

Broad introduction of the field
Present Challenges
Fabrication methods
Breakthrough publications
Significant applications

Instruction:

To improve writing skill, I highly recommend the Kristin Sainani’s course from Stanford University, . Complete week 1-5 of the course to improve your writing style.

Review Article LaTeX Template

Review Article Grading Criteria and Rubric

Title and Introduction (10 points)

Clarity and Relevance (3 points): Is the title clear and does it reflect the topic’s relevance to the course? Is the introduction engaging and informative?
Scope and Significance (3 points): Does the introduction clearly define the scope of the review article and its significance in the context of the course?
Thesis Statement (4 points): Is there a well-defined thesis statement that sets the direction for the review?

Literature Review (40 points)

Comprehensiveness (15 points): Does the literature review include a comprehensive collection of relevant sources (30-50 references)? Is the selection of sources well-justified?
Synthesis and Analysis (15 points): Does the review demonstrate the ability to synthesize and critically analyze the selected literature? Are key findings and trends identified?
Integration with Course Content (10 points): How effectively does the literature review integrate with the course content? Does it contribute to the course’s learning objectives?

Summary Figures and Tables (10 points)

Summary Figure (5 points): Is there a clear and informative summary figure that visually represents the key findings or concepts discussed in the review?
Summary Table (5 points): Is there an organized and concise summary table that highlights important details from the reviewed literature?

Organization and Clarity (15 points)

Structure (5 points): Is the article well-organized with clear sections (e.g., introduction, literature review, discussion)? Is there a logical flow of ideas?
Clarity of Expression (5 points): Is the writing clear, concise, and free from jargon? Are technical terms explained where necessary?
Transitions (5 points): Are there smooth transitions between paragraphs and sections, making it easy for the reader to follow the argument?

Quality of Figures (10 points)

Clarity and Relevance (5 points): Are the figures clear, relevant, and effectively used to support the content of the review?
Originality and Creativity (5 points): Do the figures demonstrate originality and creativity in visually presenting information?

Individual Contribution (25 points)

Contributions (15 points): Each team member’s individual contributions are clearly identified within the text. Each student’s contribution should align with their respective responsibilities.
Quality of Contribution (10 points): The individual contributions should demonstrate depth and relevance to the overall review.

Conclusion and Recommendations (10 points)

Summary (5 points): Does the conclusion effectively summarize the key findings and insights from the literature review?
Recommendations (5 points): Are there clear recommendations or implications based on the review’s findings?

References and Citations (10 points)

Accuracy (5 points): Are citations and references consistently formatted following a recognized citation style (e.g., APA, IEEE)? Are all sources properly credited?
Relevance (5 points): Are all references relevant to the topic, and do they contribute to the overall quality of the review?

Overall Quality (30 points)

Originality and Depth (10 points): Does the review exhibit original thought and in-depth analysis? Does it go beyond summarizing existing knowledge?
Engagement (10 points): Does the review article engage the reader and maintain their interest throughout?
Formatting and Aesthetics (10 points): Is the article properly formatted in the given LaTeX template and aesthetically pleasing?

Total (150 points)

Group Contribution (50 points): Assess group collaboration and whether each member fulfilled their roles and responsibilities.
Individual Contribution (25 points): Evaluate individual contributions based on the clarity and quality of each student’s work within the article.
Content and Elements (75 points): Assess the quality and completeness of the review article, including figures, tables, organization, and clarity.

Grading Scale:

135-150 points: Excellent
120-134 points: Very Good
105-119 points: Good
90-104 points: Fair
Below 90 points: Needs Improvement

A Polarization Insensitive Achromatic Metalens Operating at Two Wavelengths in Visible Regime

Sun, 01 Jan 2023 00:00:00 +0000

Biomimicry in Nanotechnology: A Comprehensive Review

Sun, 01 Jan 2023 00:00:00 +0000

Design and Performance Analysis of a c-Si Thin-Film Solar Cell Using Plasmonic Ag Nanostructures

Sun, 01 Jan 2023 00:00:00 +0000

Development of an Internet of Things based Bangla Calendar Clock

Sun, 01 Jan 2023 00:00:00 +0000

Discrete Modulated Continuous-Variable Quantum Key Distribution: Security and Noise Tolerance Enhanced by Decoy States and Effective Error Correction Protocol Integration

Sun, 01 Jan 2023 00:00:00 +0000

EEE 415 (January 2023)

Sun, 01 Jan 2023 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team “EEE 415 A (Jan 2022)”.

Introduction

The syllabus of this course has been changed and the course has been completely redesigned from grounds up.

Syllabus (as approved in 2022)

Grading Policy

Class Attendance (10%) – Class participation and attendance will be recorded in every class. 30 Marks as per university AC policy
Continuous Assessment (20%) – 1 assignment (20) – Mandatory 3 Class tests, best 2 counted (40)
Final Examination (70%)– A comprehensive term final examination will be held at the end of the Term following the guideline of the Academic Council

Weekly Schedule

As per the routine published in the Department of EEE website.

Textbooks

[Harris] Sarah Harris, David Harris – “Digital Design and Computer Architecture, ARM Edition, Morgan Kaufmann (2015) - Chapter 6,7,8

[Patterson] David A. Patterson and John L. Hennessy, “Computer Organization and Design – The Hardware / Software Interface ARM edition” Morgan Kaufmann - Chapter 1

[Zhu] Yifeng Zhu “Embedded Systems with ARM Cortex-M Microcontrollers with Assembly Language and C”

Semester Plan

Week	Lectures	Topic	Textbook
1	1-3	Fundamentals of microprocessor and computer design, processor data path, architecture, microarchitecture, introduction to CISC and RISC, complexity, metrics, and benchmark.	Patterson 1
2	4-6	Assembly Language.	Harris 6.1-6.3
3	7-9	Assembly Language Programming.	Harris 6.3
4	10-12	Machine Language, Compiling, Assembling.	Harris 6.4
5	13-15	Performance Analysis, Single Cycle and Multicycle Processor.	Harris 7.1-7.4
6	16-18	Pipelining, Hazards, Advanced Microarchitecture.	Harris 7.5,7.7
7	19-21	Memory Systems – Cache and Virtual Memory.	Harris 8.2-8.4
8	20-24	Introducing Embedded System Design, IoT, Arm Cortex m4.	Lecture Slides
9	25-27	General Purpose Input Output.	Zhu 14
10	28-30	General Purpose Timers.	Zhu 15.1-15.3
11	31-33	Interrupts.	Zhu 11, 15.4
12	34-36	ADC + DAC.	Zhu 20,21
13	37-39	Serial Communication.	Zhu 22

Reconfigurable Broadband Metasurface with Switchable Functionalities in the Visible Range

Sun, 01 Jan 2023 00:00:00 +0000

Structurally Tunable Gear-Shaped Plasmonic Sensor

Sun, 01 Jan 2023 00:00:00 +0000

VO2-based All-optical Reflection Modulator for 2$μ$m Wave Band

Sun, 01 Jan 2023 00:00:00 +0000

Comprehensive Review on Biomimicry in Nanotechnology Published

Thu, 22 Dec 2022 00:00:00 +0000

A comprehensive review titled “Biomimicry in Nanotechnology: A Comprehensive Review” has been published in Nanoscale Advances. The paper delves into how biological principles inspire the design and development of nanomaterials and devices, highlighting the intersection of biology and nanotechnology for innovative solutions.

Abdul Mukit Secures RISE Student Research Grant

Fri, 25 Nov 2022 00:00:00 +0000

Congratulations to Abdul Mukit on successfully securing funding from the RISE Student Research Grant (Call-ID: S2022-02) for his proposal “Continuous Variable Quantum Key Distribution Optimization and Enhancing an Efficient Quantum Repeater Architecture Design for Better Quantum Communication Fidelity.”

Alumni

Mon, 24 Oct 2022 00:00:00 +0000

Antenna-Systems

Mon, 24 Oct 2022 00:00:00 +0000

Computing-Systems

Mon, 24 Oct 2022 00:00:00 +0000

Embedded-Systems

Mon, 24 Oct 2022 00:00:00 +0000

Photonic-Systems

Mon, 24 Oct 2022 00:00:00 +0000

Quantum-Systems

Mon, 24 Oct 2022 00:00:00 +0000

Renewable-Systems

Mon, 24 Oct 2022 00:00:00 +0000

EEE 303 (July 2022)

Fri, 01 Jul 2022 00:00:00 +0000

EEE 303 - Digital Electronics

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

EEE 303 - Digital Electronics

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Course Outcomes

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Analyze the structure and behaviour of different types of combinational and sequential digital logic circuits	PO1	C4	Lectures, Homework	Class test, Final exam
CO2	identify the requirements of physically implementing digital electronic circuits, different logic technologies and memory circuits	PO5	C2	Lectures, Homework	Class test, Final exam
CO3	design combinational and sequential logic circuits with practical constraints using Verilog	PO3	C6	Lectures, Tutorials, Homework	Assignment Class test, Final exam

Course Outline

Week	Topic
1	Introduction to Number Systems and codes. Introduction to Boolean algebra, Introduction to VerilogHDL	Harris 1.4, 5.3, 1.5
2-3	Analysis and synthesis of digital logic circuits: Basic logic function, combinational logic design, Universal logic gates, Minimization of combinational logic, k-map	Harris 2.1-2.9
4	Programming and structural and behavioral design of digital systems using VerilogHDL, Verilog Timing analysis and test bench. Verilog synthesis with combinational logic	Harris 4
5	ALU design (Adder, Subtractor, Comparator)	Harris 5.2- Floyd 6.1-6.3
6	Decoder, encoder, Multiplexer, demultiplexer	Floyd 6.4-6.9
7	MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates, Modular combinational circuit design: pass transistor, pass gates, and their implementation in CMOS	Harris 1.7-1.8
	MIDTERM
8	Sequential circuits: different types of latches, flip-flops	Harris 3.1-3.2 Floyd 7.1-7.3
9	Modular sequential logic circuit design: shift registers, counters, and application	Floyd 8.1-8.3, 9.2-9.7
10-11	Asynchronous and synchronous sequential circuits., Introducing State Machine Design, State Minimization, Mille and Moore type state machine, design of simple FSM using Verilog	Harris 3.4
12-13	Design of a Simple-As-Possible (SAP) computer: SAP-1, selected concepts from SAP-2 (jump, call, return)	Malvino Ch10,11 (partially)
13	Dual Inline Packaged and Surface Mount Device (SMD) Integrated Circuits, Introduction to System Integration and Printed Circuit Board design, Memories: classification and architecture, RAM memory cells, Read only memory	Lecture Slides Harris 5.5

Textbooks

[Harris] Digital Design and Computer Architecture ARM Edition
[Brown] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design” 3rd Edition, McGraw Hill (2014)
[Floyd] Thomas L. Floyd, “Digital Fundamentals” 11th Edition, Pearson (2015)
[Mano] Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL” 5th Edition, Pearson (2013)
[Malvino] Albert P. Malvino, Jerald A. Brown - Digital Computer Electronics-McGraw-Hill (1993)

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

EEE 304 (July 2022)

Fri, 01 Jul 2022 00:00:00 +0000

EEE 304 - Digital Electronics Laboratory

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

Course Outline

Week 1 - Introduction to EEE 304 Lab
Week 2 - Experiment No. 01:Introduction to Basic Gates and Logic Simplification Techniques
Week 3 - Experiment No. 02: Introduction to Digital Circuit Design Concept in FPGA
Week 4 - Experiment No. 03: Design and implementation of different adder, subtractor and comparator circuits.
Week 5 - Experiment No. 04: Design of Decoder/Encoder/Multiplexer circuit
Week 6 - Experiment No. 05: Design of Arithmatic Circuits Using Verilog and Implementation In FPGA
Week 7 - Lab Test 1
Week 8 - Experiment No. 06: Design, Simulation and Test of Comibnation Circuits Using Verilog and Implementation In FPGA
Week 9 - Experiment No. 07: Sequential circuit design –Latch, Flip-flop and Registers
Week 10 - Experiment No. 08: Design, Simulation And Test of Sequential Circuits Using Verilog and Implementation In FGPA.
Week 11 - Labtest 2
Week 12 - Final Quiz
Week 13 - Final Project Submission

EEE 6505 Nanophotonics and Plasmonics (April 2022)

Fri, 01 Apr 2022 00:00:00 +0000

Welcome

Class Schedule

Sunday 5pm-8pm

Background

This course would introduce graduate students to the field of Nanophotonics and its great wonders. We will talk about light-matter interaction in the nanoscale, how to make devices that goes beyond the diffraction limit, their theory, application and design.

Syllabus

Suggested Text Books

John D. Joannopoulos, Steven G. Johnson, Joshua N. Winn, and Robert D. Meade, Photonic Crystals: Molding the Flow of Light second edition (Princeton Press, Freely available at )
Stephen A Maier, Plasmonics: Fundamentals and Applications,
Wenshan Cai, Vladimir Shalaev, Optical Metamaterials: Fundamentals and Applications,

Grading criteria

Midterm Presentation - 30% (15 minutes presentation and Q A by the students on a relevant paper.)
Final Report - 40% (For final report, you must do a comprehensive literature review on a particular topic relevant to the course and write a 1600 word review on it, with around 20-30 literature references. The goal is to combine multiple reports and to form a scientific review article on a particular focus (will discuss more on class))
Final Presentation - 10% (15 minutes power point presentation highlighting your final report)
Final Examination - 20% (Primarily focus on very basic concepts of the course and class discussions)

Expectation

Lesson Plan

(Subject to change based on student interest and class discussion)

Week 01 – Introduction

Week 02 – Light-Matter Interaction I

Week 03 – Light-Matter Interaction II

Week 04 – Photonic Crystals I

Week 05 – Photonic Crystals II

Week 06 – Discussion on Mid Term Presentation and Final Project

Week 07 – Mid Term Presentation I

Week 08 – Mid Term Presentation II

Week 09 – Metal Optics I

Week 10 – Metal Optics II

Week 11 – Applications of Plasmonics

Week 12 – Metamaterials

Week 13 – Final Project - I

Week 14 – Final Project - II

Midterm Presentation

Each student 10 minute presentation and 5 minutes question answer (points will be deducted for more than 12 minutes presentation) Send me a video recording. Recording will be played and Q&A will be Live. All students must attend the talks and participate in question answering.

Tentative grading rubric:

Clarity of presentation: 20
Demonstration that you understood the concept: 10
Broad introduction of the topic: 10
Explanation of results: 10
Ability to face questions on the presentation: 10
Active Participation in other presentations: 40
Attending each presentation: 20

Active participation: (you have to ask at least 4 questions in other presentations)

Final Project

For the final project of the course, you need to work in a group to write an original comprehensive review on any topic related to the course material. The review itself needs to be novel (no similar review should exist in literature).

Scope of write up (including but not limited to):

Broad introduction of the field
Present Challenges
Fabrication methods
Breakthrough publiactions
Significant applications

Instruction:

To improve writing skill, I highly recommend the Kristin Sainani’s course from Stanford University, . Complete week 1-5 of the course to improve your writing style.

Custom Gold-Patterned Rewritable Optical Disc based Plasmonic Sensor for Blood Hemoglobin Detection

Sat, 01 Jan 2022 00:00:00 +0000

EEE 415 (January 2022)

Sat, 01 Jan 2022 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team “EEE 415 A (Jan 2022)”.

Introduction

The syllabus of this course has been changed and the course has been completely redesigned from grounds up.

Syllabus (as approved in 2022)

Grading Policy

Class Attendance (10%) – Class participation and attendance will be recorded in every class. 30 Marks as per university AC policy
Continuous Assessment (20%) – 1 assignment (20) – Mandatory 3 Class tests, best 2 counted (40)
Final Examination (70%)– A comprehensive term final examination will be held at the end of the Term following the guideline of the Academic Council

Weekly Schedule

Sat 12pm
Wed 9am
Wed 10am

Textbooks

[Harris] Sarah Harris, David Harris – “Digital Design and Computer Architecture, ARM Edition, Morgan Kaufmann (2015) - Chapter 6,7,8

[Patterson] David A. Patterson and John L. Hennessy, “Computer Organization and Design – The Hardware / Software Interface ARM edition” Morgan Kaufmann - Chapter 1

[Zhu] Yifeng Zhu “Embedded Systems with ARM Cortex-M Microcontrollers with Assembly Language and C”

Semester Plan

Week 01 - Introduction (Patternson Ch1)
Week 02 - Assembly Language (Harris Ch6)
Week 03 - Architecture (Harris Ch6)
Week 04 - MicroArchitecture, Single Cycle Computer (Harris Ch7)
Week 05 - Pipelining, (Harris Ch7)
Week 06 - Advanced Microarchitectures (Harris Ch7)
Week 07 - Memory (Harris Ch8)
Midterm
Week 8-14 TBA

EEE 416 (January 2022)

Sat, 01 Jan 2022 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team.

Introduction

The syllabus of this course has been changed and the course has been completely redesigned from grounds up. There has been a lab development proposal that is under consideration with the University authority. We anticipate changing to FPGA based Microprocessor design and ARM/RISC-V Microcontroller based embedded systems design. As procurement is a time-consuming process, we might need to improvise and use existing lab infrastructure for this semester.

Syllabus (as approved in 2022)

TiN-GST-TiN all-optical reflection modulator for the 2$μ$m wave band reaching 85% efficiency

Sat, 01 Jan 2022 00:00:00 +0000

Thermophotovoltaic system and method of making the same

Thu, 29 Jul 2021 00:00:00 +0000

EEE 303 (July 2021)

Thu, 01 Jul 2021 00:00:00 +0000

EEE 303 - Digital Electronics

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

EEE 303 - Digital Electronics

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Course Outline

Week 1 - (Brown 5.1, 5.7, 2.10, Floyd 2.1-2.10) - Introduction to Course, Introduction to Number Systems and codes. Introduction to verilog
Week 2 - (Floyd 3.1-3.7,4 Brown 2.1-2.9) - Analysis and synthesis of digital logic circuits: Basic logic function, Boolean algebra, combinational logic design, minimization of combinational logic (k-map)
Week 3 - (Floyd 3.1-3.7,4 Brown 4.1-4.5) Boolean algebra, combinational logic design, Minimization of combinational logic (k-map)
Week 4 - (Floyd 5, Brown 2.7,2.10, 5.2-5.4, 5.6 supplimentary) Universal logic gates, binary arithmetic elements and ALU design, Verilog synthesis with combinational logic
Week 5 - (Brown 6.1-6.6, Floyd 6) Decoder, encoder, comparators,
Week 6 - (Brown 7.1-7.15) Sequential circuits: different types of latches, flip-flops, Modular sequential logic circuit design: shift registers, counters, and application, timing analysis and power optimization of sequential circuits.
Week 7 - Completing topics of week6, Classtests and Revision
Week 8 - (Brown 8.1-8.8, Brown 8) - Synchronous sequential circuits, State Machine Design, Algorithmic State Machine (ASM)
Week 9 - ,
Week 10 - (Floyd 11) Asynchronous sequential circuits, Pass Transistor
Week 11 - (Floyd 15) MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates, sequential logic circuits,
Week 12 - (Brown 6.1) BJT digital circuits: ECL, TTL, STTL, BiCMOS
Week 13 - Memories: classification and architecture, RAM memory cells, Read only memory, data converters,

Textbooks

Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”
Thomas L. Floyd, “Digital Fundamentals Eleventh Edition”
Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL”

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

EEE 304 (July 2021)

Thu, 01 Jul 2021 00:00:00 +0000

EEE 304 - Digital Electronics Laboratory

For latest announcements and updates, please refer to the Class Team in your Microsoft Teams account. Please contact me if you have not been added to the class Team.'

Course Outline

Week 1 - Introduction to EEE 304 Lab
Week 2 - Experiment No. 01:Introduction to Basic Gates and Logic Simplification Techniques
Week 3 - Experiment No. 02: Introduction to Digital Circuit Design Concept in FPGA
Week 4 - Experiment No. 03: Design and implementation of different adder, subtractor and comparator circuits.
Week 5 - Experiment No. 04: Design of Decoder/Encoder/Multiplexer circuit
Week 6 - Experiment No. 05: Design of Arithmatic Circuits Using Verilog and Implementation In FPGA
Week 7 - Lab Test 1
Week 8 - Experiment No. 06: Design, Simulation and Test of Comibnation Circuits Using Verilog and Implementation In FPGA
Week 9 - Experiment No. 07: Sequential circuit design –Latch, Flip-flop and Registers
Week 10 - Experiment No. 08: Design, Simulation And Test of Sequential Circuits Using Verilog and Implementation In FGPA.
Week 11 - Labtest 2
Week 12 - Final Quiz
Week 13 - Final Project Submission

EEE 6505 Nanophotonics and Plasmonics (April 2021)

Thu, 01 Apr 2021 00:00:00 +0000

Welcome

Announcement

Here is a link to the first class:

Time: Jul 24, 2021 05:30 PM Astana, Dhaka

Background

Syllabus

Suggested Text Books

John D. Joannopoulos, Steven G. Johnson, Joshua N. Winn, and Robert D. Meade, Photonic Crystals: Molding the Flow of Light second edition (Princeton Press, Freely available at )
Stephen A Maier, Plasmonics: Fundamentals and Applications,
Wenshan Cai, Vladimir Shalaev, Optical Metamaterials: Fundamentals and Applications,

Grading criteria

Midterm Presentation - 30% (15 minutes presentation and Q A by the students on a relevant paper.)
Final Report - 40% (For final report, you must do a comprehensive literature review on a particular topic relevant to the course and write a 1600 word review on it, with around 20-30 literature references. The goal is to combine multiple reports and to form a scientific review article on a particular focus (will discuss more on class))
Final Presentation - 10% (15 minutes power point presentation highlighting your final report)
Final Examination - 20% (Primarily focus on very basic concepts of the course and class discussions)

Expectation

Lesson Plan

(Subject to change based on student interest and class discussion)

Week 01 – Introduction

Week 02 – Light-Matter Interaction I

Week 03 – Light-Matter Interaction II

Week 04 – Photonic Crystals I

Week 05 – Photonic Crystals II

Week 06 – Discussion on Mid Term Presentation and Final Project

Week 07 – Mid Term Presentation I

Week 08 – Mid Term Presentation II

Week 09 – Metal Optics I

Week 10 – Metal Optics II

Week 11 – Applications of Plasmonics

Week 12 – Metamaterials

Week 13 – Final Project - I

Week 14 – Final Project - II

Midterm Presentation

Tentative grading rubric:

Clarity of presentation: 20
Demonstration that you understood the concept: 10
Broad introduction of the topic: 10
Explanation of results: 10
Ability to face questions on the presentation: 10
Active Participation in other presentations: 40
Attending each presentation: 20

Active participation: (you have to ask at least 4 questions in other presentations)

Final Project

Scope of write up (including but not limited to):

Broad introduction of the field
Present Challenges
Fabrication methods
Breakthrough publiactions
Significant applications

Instruction:

To improve writing skill, I highly recommend the Kristin Sainani’s course from Stanford University, . Complete week 1-5 of the course to improve your writing style.

A Review on Plasmonic and Metamaterial Based Biosensing Platforms for Virus Detection

Fri, 01 Jan 2021 00:00:00 +0000

Design and Low-cost Fabrication of Optical Biosensors for Virus Detection

Fri, 01 Jan 2021 00:00:00 +0000

EEE 415 (January 2021)

Fri, 01 Jan 2021 00:00:00 +0000

Announcement

This website is not going to be updated. For online classes, we have migrated to the Institutional Microsoft Teams account. Please contact me if you have not been added to the class Team.'

Schedule

Sat 9pm
Mon 9pm
Wed 10am

EEE 416 (January 2021)

Fri, 01 Jan 2021 00:00:00 +0000

Announcement

This website is not going to be updated. For online classes, we have migrated to the Institutional Microsoft Teams account. Please contact me if you have not been added to the class Team.'

EEE 416 (January 2023)

Fri, 01 Jan 2021 00:00:00 +0000

Announcement

We will use Microsoft Teams for disbursing class materials for the course. Please contact your respective course instructor if you have not been added to the class team.

2023Introduction

In the 2023 syllabus the 416 course will be heavily project focused. We will use the project of EEE 416 as a primary replacement of the Capstone Project, for culmination of program outcomes.

Syllabus

EEE 416

EEE 415

Course Objectives

To perform experiments in relevance with the theoretical concepts of the course EEE 415: Microprocessor and Embedded Systems
To conduct design projects in order achieve specific program outcomes described in the Course Outline

Course Outcomes

Upon successful completion of the course, students will be able to

CO No.	CO Statement	Corresponding PO(s)*	Domains and Taxonomy level(s)**	Delivery Method(s) and Activity(-ies)	Assessment Tool(s)
CO1	Utilize VerilogHDL, ARM assembly, C programming and microcontrollers boards for implementing and analyzing theoretical concepts at software and hardware levels	PO(e)	P4, C4	–	Lab Performance, Lab Test, Quiz, Viva, Project
CO2	Design an embedded system with appropriate considerations to safety, cultural, societal, and environmental considerations	PO(c)	C6	–	Project Report and Hardware demonstration
CO3	Assess impact of embedded systems project design on Societal, Health, Safety, Legal and Cultural Issues	PO(f)	C5	–	Presentation and Report
CO4	Evaluate Sustainability the and Impact of the Designed embedded systems Project in the Societal and Environmental Contexts	PO(g)	C5	–	Presentation and Report
CO5	Demonstrate membership and leadership in designing embedded system related problem solving	PO(i)	P7	–	Project logbook , Peer assessment, Viva, Presentation
CO6	Communicate effectively on embedded system related design with presentation and detailed report	PO(j)	A2	–	Video Presentation, Design Report
CO7	Demonstrate project management and cost analysis for embedded system project	PO(k)	A3	–	Project Report and Presentation

For details of program outcome (PO) statements, please see the departmental website or course curriculum _

KPA Mapping

Weekly Plan

Week	Mode	Topic
1	Experiment 00	Introduction to Lab, Lab Policies and Tools
2	Experiment 01	Arm Cortex M: GPIO: Interfacing LED, Push-Button and Stepper Motor	CO1 (PO(e))
3	Experiment 02	Arm Cortex M: Interrupt and Timers I	CO1 (PO(e))
4	Experiment 03	Arm Cortex M: Interrupt and Timers II	CO1 (PO(e))
5	Presentation	· Project Proposal Presentation · Describe specific technical requirements to be attained during the project · Describe sustainability and impact of the work in societal and environmental contexts	CO4 (PO(g))
6	Experiment 04	Arm Cortex M: Analog Interfacing	CO1 (PO(e))
7	Experiment 05	Arm Assembly Language and Architecture	CO1 (PO(e))
8	Experiment 06	Arm Micro Architecture: Single Cycle, Multi Cycle and Pipelining	CO1 (PO(e))
9	Project Progress Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-1 · Present/demonstrate the technical progress of the project · Describe contextual knowledge to assess societal, health, safety, legal and cultural issues relevant to the project	CO2 (PO(c)) CO4 (PO(f))
10	Assessment	Lab Test	CO1 (PO(e))
12	Lab Quiz and Viva	Sessional Quiz	CO1 (PO(e)) CO2 (PO(c))
11	Project Demonstration/ Presentation	· Project Progress Demonstration/ Presentation-2 · Present/demonstrate the technical progress of the project · Describe multidisciplinary aspects of the project · Describe how each team member has been effectively working (individually and as a member or leader) to attain the goals (Self- and peer-assessment of students)	CO5 (PO(c) CO7 (PO(i))
13	Final Presentation	· Describe how engineering management principles and economic decision-making applied to the project · Use multimedia and necessary documentation (user manual, video demonstration and project report) to clearly communicate the project	CO7 (PO(k)) CO6 (PO(j))
14	Project Demonstration	· Practical demonstration of the project: show evidence that specific technical requirements have been attained by the project	CO2 (PO(c))

Distribution of Marks

Class Participation and Attendance 10%
Lab Reports 5%
Lab Experiments 10%
Lab Test 15%
Sessional Quiz 15%
Final Project 45%
Total 100%

Lab Usage Policy

No Food or Drink is allowed in the laboratory.
At the beginning of each lab, please check out the “Embedded Systems Kit” box from Mr. Selim, writing your name and information in logbook. Please check individually if each component is in the box.
Report any missing parts at the beginning of the lab.
You will be financially responsible for unreported missing items
Do not separate / tear the jumper cable collection.
Before connecting the USB port, double check the power and ground connection of your externally connected components.

T Grating on Nano-Cavity Array based Refractive Index Sensor

Fri, 01 Jan 2021 00:00:00 +0000

EEE 303 (January 2020)

Wed, 01 Jan 2020 00:00:00 +0000

Announcement

This website is not going to be updated. For online classes, we have migrated to the Institutional Microsoft Teams account. Please contact me if you have not been added to the class Team.'

Welcome

“There are 10 types of people in this world. Those who understand binary, and those who doesn’t.”

Welcome to the course on Digital Electronics, where we will explore the very fundamental concepts that makes most of our modern consumer electronic products function.

Office Hours

Tues 12-1pm (Section A) Saturday 12-1pm (Section B) I will be in my office at EEE 222, and students are welcome to drop by with any questions/problems related to the class or for conceptual understanding of the topics. Other than office hours, prior appointment must be made to schedule a meeting. For any course related matter outside the class, preferred medium of communication is email

Course Outline

Week 1 - (Brown 5.1, Floyd 2.1-2.10) - Introduction to Course, Introduction to Number Systems and codes. Introduction to verilog
Week 2 - (Floyd 3.1-3.7,4 Brown 2.1-2.9) - Analysis and synthesis of digital logic circuits: Basic logic function, Boolean algebra, combinational logic design, minimization of combinational logic (k-map)
Week 3 - (Floyd 5, Brown 4) universal logic gates, verilog synthesis with combinational logic
Week 4 - (Floyd 6, Brown 7) Decoder, encoder, comparators, binary arithmetic elements and ALU design
Week 5 - (Brown 7, Floyd 7) Sequential circuits: different types of latches, flip-flops
Week 6 - (Brown 7) Modular sequential logic circuit design: shift registers, counters, and application
Week 7 - (Brown 9.1-9.3, 8.1) Asynchronous and synchronous sequential circuits
Week 8 - (Brown 7.15, Brown 8) State Machine Design, Algorithmic State Machine (ASM), timing analysis and power optimization of sequential circuits.
Week 9 - MOSFET Digital circuits: NMOS inverter, CMOS inverter, CMOS logic circuits, Clocked CMOS logic circuits, transmission gates,
Week 10 - (Floyd 11) Memories: classification and architecture, RAM memory cells, Read only memory, data converters
Week 11 - (Floyd 15) BJT digital circuits: ECL, TTL, STTL, BiCMOS, Design application A static ECL gate
Week 12 - (Brown 6.1) Modular combinational circuit design: pass transistor, pass gates, multiplexer, demultiplexer and their implementation in CMOS

Lecture Notes

The lecture slides for this offering are no longer available online.

Lecture 1 - Introduction
Lecture 2,3 - Number systems and codes
Lecture 4,5,6 - Boolean Algebra, K-map, Boolean Analysis and Synthesis
Lecture 7,8 - Verilog syntax, universal gates
Lecture 9 - Classtest 1 - 1pm

Classtest Syllabus

Classtest 1

Contents of Week 1 and Week 2 from above.

Homework Problems

N.B. - Please write the following on the top of the homework:

Name:

Student ID:

Course Number: EEE 303

Course Instructor: Dr. Sajid Muhaimin Choudhury

Homework Number: 1A Date of Submission: XX

Homework 1A

An alien species have landed on earth that have four hands with 9 fingers on each hand (36 fingers in total). They follow a base-36 number system. We will define variable ‘X’ and variable ‘Y’ in their number system. The first 3 letters of your first name is variable X, last 3 letters of your last name is variable Y, first letter of your last name is variable Z (For example for Mahbubur Rahman, X=MAH, Y=MAN, Z=R, X,Y,Z are in base-36)

Problem 1: Convert X and Y to decimal, binary, hexadecimal and octal number

Problem 2: In binary and decimal, compute X+Y, X-Y. Compute 2’s complement of Y in binary and recompute X-Y

Problem 3: Represent the floating point number X.Y in IEEE single precision floating point number

Problem 4: Convert X to grey code and ASCII

Problem 5: Install Altera Quartus. Show the value of Z in Binary and hexadecimal. Attach a printed copy of the waveform with your file

Homework 1B

Problem 1: Convert Z from problem 1 into binary and take the first 8 bits from the MSB. Assume the function f(A,B,C) is defined as these first 8 bits denoted by ‘G’. Write the truth table of the function, write the function in terms of Sum of Products and Product of Sum form, and draw a K-map of the function and reduce it to minimum form.

Problem 2: Write a verilog code that generates fibonacci sequence of a number. ( )

Fibonacci number, F_n = F_(n-1) + F_(n-2); F_0 = 1; F_1 = 1

Input: clock Output: 16 bit fibonacci number

each time clock changes state from 0 to 1, the fibonacci number output is changed, showing from F_0, F_1, F_2 etc.

Case 1: F_0 = 1; F_1 = 1; (Regular fibonacci number) Case 2: F_0 = G; and F_1 = 1;

Show (print) output for both cases for 16 different clock changes

Textbooks

Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”
Thomas L. Floyd, “Digital Fundamentals Eleventh Edition”
Morris Mano and Michael Ciletti, “Digital Design with an Introduction to VerilogHDL”

Additional Resources

Proteus Tutorial:
Verilog Tutorial:
Springer has a free book available to download from there website ( ) called Introduction to Logic Circuits & Logic Design with Verilog by B. J. LaMeres (DOI:https://doi.org/10.1007/978-3-030-13605-5_8). We will teach some of the lectures from this book as it has very intuitive approach to a lot of the problems.

Structurally Tunable Gear-Shaped Plasmonic Sensor

Wed, 01 Jan 2020 00:00:00 +0000

EEE 6408 Nano Systems (October 2019)

Tue, 01 Oct 2019 00:00:00 +0000

Welcome

Welcome to the course on EEE 6408 Nano Systems

Background

As a PhD student, I had the privilege to work in the Birck Nanotechnology Center, that housed the largest academic cleanroom in the world at its inception. I had the opportunity to gain hands on experience in nanofabrication and characterization, and would be happy to share my knowledge and experience amongst young researchers and scholars. At the same time, the field of Nano Systems is rapidly developing, and the students of the course need to stay uptodate with the current trends and the state of the art.

Learning Objectives

In this course we would learn about different aspects of Nano Systems. The thrust of the course focus would be in two directions. In first thrust, we will learn about Nano fabrication techniques (lithography, ion milling, etching, vaccum deposition etc), nano measurements and characterization techniques (SEM, XRD, TEM, Optical characterization). Second thrust, we will explore recent advances of Nano Systems such as nano biosensors, nanophotonic systems, nano electro-mechanical systems (NEMS) etc. The course would focus more on developing review of scholarly articles and scientific communication of such articles.

Grading criteria

Midterm Presentation - 30% (15 minutes presentation and Q A by the students on a relevant paper.)
Final Report - 40% (For final report, you must do a comprehensive literature review on a particular topic relevant to the course and write a 1600 word review on it, with around 20-30 literature references. The goal is to combine multiple reports and to form a scientific review article on a particular focus (will discuss more on class))
Final Presentation - 10% (15 minutes power point presentation highlighting your final report)
Final Examination - 20% (Primarily focus on very basic concepts of the course and class discussions)

Expectation

It would be expected that by the end of the course, you are able to do a comprehensive review on a particular topic of interest and are able to communicate it orally. Regular participation in class discussion is strongly encouraged. Although, preparing the class presentations and report would demand time and effort, hopefully, by successful completion of the work, you would have a publishable work, and we can discuss at the end of the semester if we can compile and publish the work.

Announcement

No class on 17th March 2020

Schedule

Lectures: Tuesday 5:00-7:30pm ECE 632
Office Hour: Tuesday 2:00-5:00pm ECE 222
Midterm presentation - 7/4/2020
Final presentation - 2/6/2020, 9/6/2020
Final report due - 2/6/2020

Course Outline

(depending on the interest of the class the outline will be modified during the semester. Students are encouraged to suggest topics of interest during the semester.)

Nanosystems and Devices: Introduction- nanomaterials, nanodevices, nanostructures.
Nanoscale Lithography: X-ray, Electron-Beam and Ion-Beam; Soft Lithography; Scanning Probe Lithography.
Advances in Device Technology: nanoscale silicon devices, process technology, present challenges.
Self-Assembled Nanocrystals: self-assembly, surface defects and passivation, structures, energy levels, transitions, luminescence and lasing.
Nano Electro Mechanical Systems (NEMS): stress in thin films, mechanical to electrical transduction, surface engineering techniques, process flow, NEMS actuators, high aspect ratio system technology.
Nano Biotechnology: scope and dimensions; detection of biological species on electrical, mechanical and optical criteria; Bio functionality on silicon; Biochip sensors and systems- structures, process technology.
Nanophotonic systems
Miscelleneous topics of interest

Tentative topics on Final Presentation

Nanophotonic systems
Nanobiotechnology
NEMS
Nano energy harvesting
Metasurface
Biomimicry in nanotechnology
Emerging nano manufacturing technology
Self assembled nano-crystals
Fabrication of Neuromorphic Computers

Scope of write up (including but not limited to):

Broad introduction of the field
Present Challenges
Fabrication methods
Breakthrough publiactions
Significant applications

Instruction:

You need to form groups of 3 students. Each group will work on a particular scope. I will circulate a google form where you can give choice regarding the topics. Each group’s broad topic should be unique.

To improve writing skill, I highly recommend the Kristin Sainani’s course from Stanford University, . Complete week 1-5 of the course to improve your writing style.

If you choose to do so, I am willing to work on the final paper further with the possibility of publishing it in a peer-reviewed journal.

Lecture Plan (will update as the semester progresses)

- 25/2/2020 - Introduction to Nanotechnology and Nano Systems

Colors with plasmonic nanostructures: A full-spectrum review

Tue, 01 Jan 2019 00:00:00 +0000

Enhancing sensitivity to ambient refractive index with tunable few-layer graphene/hBN nanoribbons

Tue, 01 Jan 2019 00:00:00 +0000

Modulating Phase by Metasurfaces with Gated Ultra-thin TiN Films

Tue, 01 Jan 2019 00:00:00 +0000

Roadmap on metasurfaces

Tue, 01 Jan 2019 00:00:00 +0000

System for producing ultra-thin color phase hologram with metasurfaces

Tue, 24 Apr 2018 00:00:00 +0000

Bi-anisotropic homogenization for efficient metasurface design (invited)

Mon, 01 Jan 2018 00:00:00 +0000

Material platforms for optical metasurfaces

Mon, 01 Jan 2018 00:00:00 +0000

Hybrid plasmonic waveguides formed by metal coating of dielectric ridges

Sun, 01 Jan 2017 00:00:00 +0000

Novel Hard Mask Fabrication Method for Hybrid Plasmonic Waveguide and Metasurfaces

Sun, 01 Jan 2017 00:00:00 +0000

Pancharatnam–Berry Phase Manipulating Metasurface for Visible Color Hologram Based on Low Loss Silver Thin Film

Sun, 01 Jan 2017 00:00:00 +0000

Controlling the Polarization State of Light with Plasmonic Metal Oxide Metasurface

Fri, 01 Jan 2016 00:00:00 +0000

Experimental Realization of Color Hologram Using Pancharatnam-Berry Phase Manipulating Metasurface

Fri, 01 Jan 2016 00:00:00 +0000

Color Hologram Generation Using a Pancharatnam-Berry Phase Manipulating Metasurface

Thu, 01 Jan 2015 00:00:00 +0000

GZO/ZnO Multilayered nanodisk metasurface to engineer the plasma frequency

Wed, 01 Jan 2014 00:00:00 +0000

Nanostructured Transparent Conducting Oxide Films for Polarization Control with Plasmonic Metasurfaces

Wed, 01 Jan 2014 00:00:00 +0000

Self-localization of a mobile robot using monocular vision of a chessboard pattern

Wed, 01 Jan 2014 00:00:00 +0000

EEE Courses before Fall 2013

Tue, 01 Oct 2013 00:00:00 +0000

Courses I taught before Fall 2013

Files hosted in box.com

Multiport Analysis of Hexagonal Patch Antenna

Tue, 01 Jan 2013 00:00:00 +0000

Effect of FSS ground plane on second iteration of hexaflake fractal patch antenna

Sun, 01 Jan 2012 00:00:00 +0000

Approximate Closed-Form Expression of the Electric Field of a Conical Horn Antenna

Sat, 01 Jan 2011 00:00:00 +0000

Design and optimisation of a novel dual-band circularly polarised microstrip antenna

Sat, 01 Jan 2011 00:00:00 +0000

Developing A Low-Cost Multiple Motor Switched Photovoltaic Powered Irrigation System

Sat, 01 Jan 2011 00:00:00 +0000

Phased Array Synthesis Using Modified Particle Swarm Optimization

Sat, 01 Jan 2011 00:00:00 +0000

A Novel Approach for Changing Bandwidth of FSS Filter Using Gradual Circumferential Variation of Loaded Elements

Fri, 01 Jan 2010 00:00:00 +0000

Design of an X band aperture matched horn antenna by optimization of back-lobe and cross-polarization level

Fri, 01 Jan 2010 00:00:00 +0000

Optimization and analysis of a Ka band Pickett Potter horn antenna with low cross polarization

Fri, 01 Jan 2010 00:00:00 +0000

Sensitivity analysis of a circularly polarized U-slot microstrip antenna

Fri, 01 Jan 2010 00:00:00 +0000

IICT 5101 - Programming Concepts (Fall 2009)

Thu, 01 Oct 2009 00:00:00 +0000

Course Outline

This course introduces students to programming and logic flow, procedural versus object oriented programming, data types, variables, constants, operators, expressions, input-output, control structures, arrays, functions, pointers, file access, structures, dynamic memory allocation, classes, objects, constructor and destructor, inheritance, polymorphism, files, exception handling, etc. The course prepares students to solve basic programming problems. The course includes continuous assessment in the form of assignments, class test, and examinations.

Course Materials

IICT 5305 - Mobile Communication (Fall 2009)

Thu, 01 Oct 2009 00:00:00 +0000

Course Outline

Course Materials

Analysis of a conical corrugated horn operating in the K-band with low cross-polarization and high aperture efficiency, and observing its radiation patterns

Thu, 01 Jan 2009 00:00:00 +0000

Modeling the illumination function of a cassegrain reflector for a corrugated horn feed and calculation of the far field pattern

Thu, 01 Jan 2009 00:00:00 +0000

Design and implementation of a low cost Power Factor Improvement device

Tue, 01 Jan 2008 00:00:00 +0000

SAJID Lab

LOR Request

Foreword

Criteria for Getting Recommendation

Sample question and answer that I need to do for a LOR

List of Eligible Students

Limit of LOR Request

Waiver of Access

Steps to Get LOR:

Reply template for ineligible students

Reply template for eligible students

Poems

শান্তির সন্ধানে

বাংলাদেশের সনেট

Hobbies

Photography

Music

Website Development

Organizing Microsoft Teams Assignment Submissions with PowerShell

1. Open the class Team in SharePoint

2. Open Site contents

3. Open Student Work → Submitted Files

4. Download the submissions

5. Create the PowerShell script

6. Set the source and output folders

7. Open PowerShell in the folder

8. Run the script

If PowerShell blocks the script

The resulting folder structure

What the script does

Identifies the student

Creates one folder per assignment

Detects submission versions

Keeps the original filename

Keeps the original download unchanged

Prevents silent overwrites

Why reorganize submissions this way?

Before deleting anything from SharePoint

Complete workflow

References

EEE 6516 (October 2026)

Course Information

Syllabus

Course Content

Prerequisites

Course Outcomes (CO)

Weekly Plan

Assessment

Grading Policy

Assessment Milestones

Midterm Assignment and Final Project

Late Submission

Policies

Incomplete Grade Policy

Make-up Class Test Policy

Academic Integrity and Generative AI

Textbooks and Resources

Course Materials

Textbook

Further Reading

Software

Why Should an EEE Graduate Student Take This Course?

OMRFlow

Motivation

What it does

Status

Instructions to Hardware: A Gentle Introduction to Computer Architecture, ARM Assembly, and Verilog

Table of Contents

1. Workshop Overview

2. Learning Objectives and Scope

3. Required Software

3.1 Software and official pages

3.2 Install MSYS2

3.3 Update the package database and installed packages

3.4 Install the workshop packages

3.5 Verify the installation

3.6 Create a workshop folder

4. Workshop Files

4.1 Required processor files

4.2 Files students create or generate during the workshop

10. Machine Code and `memfile.dat`

11.3 Example: `ADD R3, R1, R2`

18. Hands-on 3B — Generate `memfile.dat`

21.1 What `CYCLES` counts

21.3 What if only `memfile.dat` changes?

`arm-none-eabi-gcc: command not found`

`iverilog: command not found` or `vvp: command not found`

`Unable to open memfile.dat` / `$readmemh` error

`arm_single.vcd` is not created

Unknown `x` values appear